Commit Graph

129 Commits

Author SHA1 Message Date
Warner Losh
0b972ac92e Support armv7 builds for userland
Make armv7 as a new MACHINE_ARCH.

Copy all the places we do armv6 and add armv7 as basically an
alias. clang appears to generate code for armv7 by default. armv7 hard
float isn't supported by the the in-tree gcc, so it hasn't been
updated to have a new default.

Support armv7 as a new valid MACHINE_ARCH (and by extension
TARGET_ARCH).

Add armv7 to the universe build.

Differential Revision: https://reviews.freebsd.org/D12010
2017-10-05 23:01:33 +00:00
Warner Losh
06d0095e71 We don't use ARM_ARCH_6 in the tree, and haven't for a long long
time. Remove it from here. As far as I could tell, nothing in ports
use it (either __ARM_ARCH or __ARM_ARCH_6__ is used in all the
apatches). We do have a define for _ARM_ARCH_6, but it's mostly unused
(and will remain, since it isn't in this file).
2017-08-13 04:10:47 +00:00
Enji Cooper
7a6fd8dc6b Delete trailing whitespace
MFC after:	1 month
2017-08-12 21:26:46 +00:00
Ruslan Bukin
af19cc59ca Support for v1.10 (latest) of RISC-V privilege specification.
New version is not compatible on supervisor mode with v1.9.1
(previous version).

Highlights:
    o BBL (Berkeley Boot Loader) provides no initial page tables
      anymore allowing us to choose VM, to build page tables manually
      and enable MMU in S-mode.
    o SBI interface changed.
    o GENERIC kernel.
      FDT is now chosen standard for RISC-V hardware description.
      DTB is now provided by Spike (golden model simulator). This
      allows us to introduce GENERIC kernel. However, description
      for console and timer devices is not provided in DTB, so move
      these devices temporary to nexus bus.
    o Supervisor can't access userspace by default. Solution is to
      set SUM (permit Supervisor User Memory access) bit in sstatus
      register.
    o Compressed extension is now turned on by default.
    o External GCC 7.1 compiler used.
    o _gp renamed to __global_pointer$
    o Compiler -march= string is now in use allowing us to choose
      required extensions (compressed, FPU, atomic, etc).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D11800
2017-08-10 14:18:09 +00:00
John Baldwin
ea22493a46 Explicitly set the desired MIPS ABI in toolchain flags.
Specifically, set '-mabi=XX' in AFLAGS, CFLAGS, and LDFLAGS.  This permits
building MIPS worlds and binaries with a toolchain whose default output
does not match the desired TARGET_ARCH.

_LDFLAGS (which is used with LD instead of with CC) required an update as
LD does not accept the -mabi flags (so they must be stripped from LDFLAGS
when generating _LDFLAGS).  For bare uses of LD (rather than linking via
CC), the desired ABI must be set by setting an explicit linker emulation
as done in r316514 for kernels and kernel modules.

Reviewed by:	imp
Sponsored by:	DARPA / AFRL
Differential Revision:	https://reviews.freebsd.org/D10085
2017-04-07 20:02:01 +00:00
John Baldwin
5429af5f5b Don't set the MIPS endianness flags in both ACFLAGS and CFLAGS.
This should no longer be necessary after r316620 as all places that
use ACFLAGS should already be using CFLAGS.

Reviewed by:	imp
Sponsored by:	DARPA / AFRL
Differential Revision:	https://reviews.freebsd.org/D10085
2017-04-07 19:56:12 +00:00
Jung-uk Kim
982ee4e2f5 Catch up with Clang 4.0.0. 2017-03-07 19:00:27 +00:00
Ruslan Bukin
7804dd5212 Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D8529
2016-11-16 15:21:32 +00:00
Alexander Kabaev
d037279cc0 Set endianness and floating point flags explicitly for MIPS targets
The tree can be build with an external toolchain that will not
necessarily default to desired settings, so we have to specify
the required flags explicitly to force the required compilation
mode.

Reviewed by:	adrian, br
Sponsored by:	https://reviews.freebsd.org/D8505
2016-11-16 03:19:36 +00:00
Bryan Drewery
1bec4c5b3d Use proper MACHINE_ARCH.
This fixes ports on mips after r308130.
2016-11-03 19:39:32 +00:00
Ruslan Bukin
2ad1d09f16 o Add support for long double.
o Add support for latest RISC-V GNU toolchain.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-11-03 13:06:17 +00:00
Ruslan Bukin
5bca221511 Add full softfloat and hardfloat support for MIPS.
This adds new target architectures for hardfloat:
mipselhf mipshf mips64elhf mips64hf.

Tested in QEMU only.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D8376
2016-10-31 15:33:58 +00:00
Justin Hibbits
dc9b124d66 Create a new MACHINE_ARCH for Freescale PowerPC e500v2
Summary:
The Freescale e500v2 PowerPC core does not use a standard FPU.
Instead, it uses a Signal Processing Engine (SPE)--a DSP-style vector processor
unit, which doubles as a FPU.  The PowerPC SPE ABI is incompatible with the
stock powerpc ABI, so a new MACHINE_ARCH was created to deal with this.
Additionaly, the SPE opcodes overlap with Altivec, so these are mutually
exclusive.  Taking advantage of this fact, a new file, powerpc/booke/spe.c, was
created with the same function set as in powerpc/powerpc/altivec.c, so it
becomes effectively a drop-in replacement.  setjmp/longjmp were modified to save
the upper 32-bits of the now-64-bit GPRs (upper 32-bits are only accessible by
the SPE).

Note: This does _not_ support the SPE in the e500v1, as the e500v1 SPE does not
support double-precision floating point.

Also, without a new MACHINE_ARCH it would be impossible to provide binary
packages which utilize the SPE.

Additionally, no work has been done to support ports, work is needed for this.
This also means no newer gcc can yet be used.  However, gcc's powerpc support
has been refactored which would make adding a powerpcspe-freebsd target very
easy.

Test Plan:
This was lightly tested on a RouterBoard RB800 and an AmigaOne A1222
(P1022-based) board, compiled against the new ABI.  Base system utilities
(/bin/sh, /bin/ls, etc) still function appropriately, the system is able to boot
multiuser.

Reviewed By:	bdrewery, imp
Relnotes:	yes
Differential Revision:	https://reviews.freebsd.org/D5683
2016-10-22 01:57:15 +00:00
Ruslan Bukin
01a62066c3 Revert r303911 "Remove extra -msoft-float flags settings."
This was not properly tested.
2016-08-11 13:42:31 +00:00
Ruslan Bukin
2d700cb557 Remove extra -msoft-float flags settings.
This helps to build firmware modules.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-08-10 13:32:27 +00:00
Ruslan Bukin
9ddd36c20a Set the soft-float flag for assembly code as well.
This fixes compilation with GCC 6.1.

Sponsored by:	DARPA, AFRL
2016-07-22 15:22:49 +00:00
Warner Losh
2c0e9e2a09 Make armv6 hard float abi by default. Kill armv6hf.
Allow CPUTYPE=soft to build the current soft-float abi libraries.
Add UPDATING entry to announce this.

Approved by: re@ (gjb)
2016-05-18 06:01:18 +00:00
Pedro F. Giffuni
ca7f4027f7 share: minor spelling fixes.
Mostly comments but these tend to be user-visible.

MFC after:	2 weeks
2016-05-01 16:29:02 +00:00
Warner Losh
b1101485df Support simple soft floating point abi for CPUTYPE in arm. Complex
types to follow.
2016-03-28 17:32:31 +00:00
Ruslan Bukin
1fdcc5e5c0 Start support for the RISC-V 64-bit architecture developed by UC Berkeley.
RISC-V is a new ISA designed to support computer research and education, and
is now become a standard open architecture for industry implementations.

This is a minimal set of changes required to run 'make kernel-toolchain'
using external (GNU) toolchain.

The FreeBSD/RISC-V project home: https://wiki.freebsd.org/riscv.

Reviewed by:	andrew, bdrewery, emaste, imp
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4445
2015-12-11 22:55:23 +00:00
Warner Losh
fd48e7a5af Handle CPUTYPE=armv[4567]* better. gcc expects those to be either
-march=foo or -mcpu=generic-foo. Catch the armvX* case and pass
the right args for it.
2015-12-11 05:39:45 +00:00
Warner Losh
dbd69b0dc4 Add aarch64 support to CPUTYPE 2015-11-20 21:49:49 +00:00
Warner Losh
828b0885d9 Add arm CPUTYPE values typically used on FreeBSD. 2015-11-19 17:06:12 +00:00
Warner Losh
17f6dfcca0 Fix missing endif. 2015-11-19 03:55:44 +00:00
Warner Losh
129898e521 Fix mips CPUTYPE so that we can pass it through to gcc.
Keep old CPUTYPEs around for compatibility. Also include
a list of typical values for FreeBSD.

# Split out from other changes in D4155

Differential Revision: https://reviews.freebsd.org/D4155
2015-11-19 03:11:20 +00:00
Warner Losh
f894f17244 Fix URL for powerpc cpu options. Remove reference to ia64 options as
no longer relevant.
2015-11-14 06:18:50 +00:00
Warner Losh
e0874a7ea6 After consultations with the arm community, don't define softfp for
armv6. It's too ambiguous. We do use the softfp ABI for the moment on
armv6, but we allow floating point register use (and the compilers
will generate it). This is too ambiguous to use it as a decider for
which algorithms to use on the platform. Err on the side of caution
and not define it.

Submitted by: ian@
Reviewed by: andrew@
2015-08-26 17:10:43 +00:00
Warner Losh
1cdb618269 Add softfp to MACHINE_CPU more often when we're compiling for soft
float targets. It is added for booke on powerpc and all arm with hf in
the string. Also add arm to all arm builds and armv6 to armv6 and
newer builds.

PR: 202641
2015-08-25 17:11:49 +00:00
Warner Losh
d1f6fa8f71 We need to add the soft float to the CFLAGS always, not just when
NO_CPUCFLAGS is not defined since it is part of the ABI as we've
defined it, not just a nice optimization.
2015-08-24 00:03:51 +00:00
Eric van Gyzen
ddab052725 Disable SSE in libthr
Clang emits SSE instructions on amd64 in the common path of
pthread_mutex_unlock.  If the thread does not otherwise use SSE,
this usage incurs a context-switch of the FPU/SSE state, which
reduces the performance of multiple real-world applications by a
non-trivial amount (3-5% in one application).

Instead of this change, I experimented with eagerly switching the
FPU state at context-switch time.  This did not help.  Most of the
cost seems to be in the read/write of memory--as kib@ stated--and
not in the #NM handling.  I tested on machines with and without
XSAVEOPT.

One counter-argument to this change is that most applications already
use SIMD, and the number of applications and amount of SIMD usage
are only increasing.  This is absolutely true.  I agree that--in
general and in principle--this change is in the wrong direction.
However, there are applications that do not use enough SSE to offset
the extra context-switch cost.  SSE does not provide a clear benefit
in the current libthr code with the current compiler, but it does
provide a clear loss in some cases.  Therefore, disabling SSE in
libthr is a non-loss for most, and a gain for some.

I refrained from disabling SSE in libc--as was suggested--because
I can't make the above argument for libc.  It provides a wide variety
of code; each case should be analyzed separately.

https://lists.freebsd.org/pipermail/freebsd-current/2015-March/055193.html

Suggestions from:	dim, jmg, rpaulo
Approved by:	kib (mentor)
MFC after:	2 weeks
Sponsored by:	Dell Inc.
2015-08-05 12:53:55 +00:00
Andrew Turner
5607ec2379 Set MACHINE_CPU to arm64 when building for arm64. This is needed by the
ports tree as they check this value in a number of ports.

PR:		201259
Sponsored by:	ABT Systems Ltd
2015-07-02 13:42:57 +00:00
Andrew Turner
61b9bd2303 Sort the cpu architectures by name rather than a combination of
alphabetical order and appending new architectures to the end of the list.

Obtained from:	ABT Systems Ltd
Sponsored by:	The FreeBSD Foundation
2015-06-25 16:47:11 +00:00
Jung-uk Kim
25fd8105c9 Catch up with Clang 3.6.0. 2015-03-17 05:48:45 +00:00
Ian Lepore
1d2c1366bf For armv6 builds, add -mfloat-abi=softfp. This tells the compiler it can
use floating point hardware instructions (because all armv6/7 systems we
support have fp hardware), but it passes args using a soft-float compatible
ABI.  This should give noticible performance improvement (but not as much
as using the armv6hf arch).
2015-01-19 04:56:17 +00:00
Andrew Turner
a103277891 Set the correct architecture when targeting ARMv7
MFC after:	1 Week
Sponsored by:	ABT Systems Ltd
2014-12-01 21:07:36 +00:00
Ian Lepore
cc55c7c78f Support CXXFLAGS.${MACHINE_ARCH} as well as CFLAGS. This allows different
C++ options for toolchain versus target when cross-building.
2014-07-08 14:37:01 +00:00
Marcel Moolenaar
e7d939bda2 Remove ia64.
This includes:
o   All directories named *ia64*
o   All files named *ia64*
o   All ia64-specific code guarded by __ia64__
o   All ia64-specific makefile logic
o   Mention of ia64 in comments and documentation

This excludes:
o   Everything under contrib/
o   Everything under crypto/
o   sys/xen/interface
o   sys/sys/elf_common.h

Discussed at: BSDcan
2014-07-07 00:27:09 +00:00
Jung-uk Kim
6619822598 Add new CPUTYPEs supported by Clang 3.4, i.e., AMD Steamroller (bdver3) and
Intel Silvermont (slm) processors.
2014-03-20 19:17:46 +00:00
Ian Lepore
44653522f6 Add a way to apply CFLAGS only when building the given architecture. This
is useful primarily on a system used for cross-building, when you have a
set of flags to apply to the TARGET_ARCH being cross-built but don't want
those settings applied to building the cross-tools or other components that
run on the build host machine.
2014-03-19 18:54:53 +00:00
Jung-uk Kim
cd0e2d2a92 Add a new CPUTYPE supported by Clang 3.3 for AMD Jaguar processors (btver2). 2013-06-13 18:26:12 +00:00
Olivier Houchard
755147dd88 Nuke ARM_WANT_TP_ADDRESS, it's not used anymore.
Don't force -march=armv6 for Cortex A, as we want at least armv6k. The
compiler default is good enough.
2013-01-07 23:41:14 +00:00
Jung-uk Kim
cea10e1d3b Fix typos in the previous commit. 2012-12-04 00:44:31 +00:00
Jung-uk Kim
08e90c1491 Tidy up bsd.cpu.mk for X86 CPUs:
- Do not limit recent processors to "prescott" class for i386 target.  There
is no reason for this hack because clang is default now.  On top of that, it
will only grow indefinitely over time.
- Add more CPUTYPEs, i.e., "athlon-fx", "core-avx2", "atom", "penryn", and
"yonah".  Note "penryn" and "yonah" are intentionally undocumented because
they are not supported by gcc and marked deprecated by clang.
- Add more CPUTYPE aliases, i.e., "barcelona" (-> amdfam10), "westmere" and
"nehalem" (-> corei7).  Note these are intentionally undocumented because
they are not supported by (base) gcc and/or clang.  However, LLVM (backend)
seems to "know" the differences.  Most likely, they were deprecated with
other vendor code names and clang did not bother implementing them at all.
- Add i686 to MACHINE_CPU for "c3-2" (VIA Nehemiah).  Both gcc & clang treat
it like an i686-class processor.
- Add IDT "winchip2" and "winchip-c6" for completeness (undocumented).
- Order processors per make.conf example, i.e., CPU vendors and models.
- Tidy up make.conf example, i.e., remove "by gcc" (because we have aliases)
and remove "prescott" from AMD64 architecture (because it is not correct).
2012-12-04 00:37:17 +00:00
Jung-uk Kim
04704c638e Remove fictitious support for 80386-class CPUs from bsd.cpu.mk and make(1).
It was removed from head more than 8 years ago (see r137784 and r137785).

Reviewed by:	imp, delphij, dim
2012-12-03 19:27:31 +00:00
Jung-uk Kim
49f4a268d5 Add x86 CPUs supported by clang on head.
Reviewed by:	arch (silence)
X-MFC:		r242624
2012-11-19 21:58:14 +00:00
Oleksandr Tymoshenko
4da573d910 Merging of projects/armv6, part 3
r238211:
Support TARGET_ARCH=armv6 and TARGET_ARCH=armv6eb

This adds a new TARGET_ARCH for building on ARM
processors that support the ARMv6K multiprocessor
extensions.  In particular, these processors have
better support for TLS and mutex operations.

This mostly touches a lot of Makefiles to extend
existing patterns for inferring CPUARCH from ARCH.
It also configures:
 * GCC to default to arm1176jz-s
 * GCC to predefine __FreeBSD_ARCH_armv6__
 * gas to default to ARM_ARCH_V6K
 * uname -p to return 'armv6'
 * make so that MACHINE_ARCH defaults to 'armv6'
It also changes a number of headers to use
the compiler __ARM_ARCH_XXX__ macros to configure
processor-specific support routines.

Submitted by:	Tim Kientzle <kientzle@freebsd.org>
2012-08-15 03:21:56 +00:00
Dimitry Andric
58ff0f42ba Remove support for the Intel C Compiler from the build infrastructure.
This support has not worked for several years, and is not likely to work
again, unless Intel decides to release a native FreeBSD version of their
compiler. ;)
2011-04-19 18:09:21 +00:00
Martin Matuska
432edffe38 Add ssse3 capability for CPUTYPE=core2 to MACHINE_CPU in bsd.cpu.mk
MFC after:	2 weeks
2011-03-14 13:36:51 +00:00
Martin Matuska
d93806e2f1 Add AMD Geode CPU type to bsd.cpu.mk and examples/etc/make.conf
For CPUTYPE=core2 use -march=core2

PR:		gnu/155308
MFC after:	2 weeks
2011-03-07 14:58:23 +00:00
Martin Matuska
c42ed003e9 Add opteron-sse3, athlon64-sse3 and k8-sse3 cpu types to bsd.cpu.mk.
- add "sse3" to MACHINE_CPU for the new cpu types
- for i386, default to CPUTYPE=prescott for the new cpu types

PR:		gnu/154906
Discussed with:	kib, kan, dim
MFC after:	2 weeks
2011-02-20 22:32:21 +00:00