Commit Graph

15 Commits

Author SHA1 Message Date
Marius Strobl
9d769eb369 Clear any possibly pending PCI error bits left by the firmware. These
could trigger an error interrupt that we can't actually to do anything
against as soon as enabling the error handlers.
While at it don't bother about writing only to the write-one-to-clear
bits when clearing error bits.
2008-09-18 19:45:22 +00:00
Marius Strobl
7439368f60 o Revamp the sparc64 interrupt code in order to be able to interface
with the INTR_FILTER-enabled MI code. Basically this consists of
  registering an interrupt controller (of which there can be multiple
  and optionally different ones either per host-to-foo bridge or shared
  amongst host-to-foo bridges in any one machine) along with an interrupt
  vector as specific argument for all the interrupt vectors used by a
  given host-to-foo bridge (roughly similar to registering interrupt
  sources on amd64 and i386), providing functions to enable, clear and
  disable the interrupts of the children beneath the bridge.
  This also includes:
  - No longer entering a critical section in tl0_intr() and tl1_intr()
    for executing interrupt handlers but rather let the handlers enter
    it themselves so in the case of intr_event_handle() we don't enter
    a nested critical section.
  - Adding infrastructure for binding delivery of interrupt vectors to
    specific CPUs which later on can be interfaced with the code from
    amd64/i386 for binding interrupts to specific CPUs.
  - Getting rid of the wrapper hack introduced along the lines of the
    API changes for INTR_FILTER which as a side-effect caused interrupts
    associated with ithread handlers only to get the elevated priority
    of those associated with filters ("fast handlers") (this removes the
    hack also in the non-INTR_FILTER case).
  - Disabling (by not clearing) an interrupt in the interrupt controller
    until all associated handlers have been executed, which is crucial
    for the typical locking strategy of NIC drivers in order to work
    correctly in case of shared interrupts. This was a more or less
    theoretical problem on sparc64 though, as shared interrupts are
    rather uncommon there except for the on-board SCCs and UARTs.
  Note that due to the behavior of at least of some of the interrupt
  controllers used on sparc64 an enable+EOI instead of a disable+EOI
  approach (as implied by the INTR_FILTER MI code and implemented on
  other architectures) is used as the latter can cause lost interrupts
  or in the worst case interrupt starvation.
o Correct a typo in sbus_alloc_resource() which caused (pass-through)
  allocations to only work down to the grandchildren of the bus, which
  wasn't a real problem so far as we don't support any devices which are
  great-grandchildren or greater of a U2S bridge, yet.
o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4()
  in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid
  of some other unneeded members in fhc_softc.

Reviewed by:	marcel (earlier version)
Approved by:	re (kensmith)
2007-09-06 19:16:30 +00:00
Marius Strobl
6bbb5a106c - Divorce the IOTSBs, which so far where handled via a global list
instead of per IOMMU, so we no longer need to program all of them
  identically in systems having multiple IOMMUs. This continues the
  rototilling of the nexus(4) done about 5 months ago, which amongst
  others changed nexus(4) and the drivers for host-to-foo bridges
  to provide bus_get_dma_tag methods, allowing to handle DMA tags in
  a hierarchical way and to link them with devices.
  This still doesn't move the silicon bug workarounds for Sabre (and
  in the uncommitted schizo(4) for Tomatillo) bridges into special
  bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o
  fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy()
  this still requires too much hackery, i.e. per-child parent DMA
  tags in the parent driver.
- Let the host-to-foo drivers supply the maximum physical address
  of the IOMMU accompanying the bridges. Previously iommu(4) hard-
  coded an upper limit of 16GB, which actually only applies to the
  IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants
  as well as the U2S in fact can can translate to up to 2TB, i.e.
  translate to 41-bit physical addresses. According to the recently
  available Tomatillo documentation these bridges even translate to
  43-bit physical addresses and hints at the Schizo bridges doing
  43 bits as well.
  This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on
  sparc64" was refering to and pretty much obsoletes the lack of
  support for bounce buffers on sparc64.

Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual.

Approved by:	re (kensmith)
2007-08-05 11:56:44 +00:00
Marius Strobl
d05b58ad32 o Changes to psycho_attach(): [1]
- Clear the PCI AFSR and status error bits as previous errors still
    might be indicated.
  - Set up the PCI control and diagnostic registers according to the
    capabilities, workarounds, etc of/for specific revisions of the
    supported bridges. This includes no longer setting Hummingbird-/
    Sabre-specific bits in the PCI control register but preserving
    what the firmware has initialized them to like OpenSolaris does.
    Previously we were setting these bits according to the example in
    the Sabre documentation, which I doubt is appropriate for all
    Sabre based designs and especially not for Hummingbirds. This
    also includes not enabling bus parking unless the firmware tells
    us to.
  - Set the PCI latency timer register as this isn't always done by
    the firmware.
o Remove a redundant argument from psycho_set_intr() and in this
  function check the return value of bus_setup_intr(). [2]
o Let psycho_setup_intr() return ENOMEM instead of 0 when it can't
  allocate memory for the interrupt wrapper stub and EINVAL instead
  of 0 if it can't find the interrupt vector in the interrupt map.
o Add a workaround for a bug of the Sabre-APB-combination where it
  doesn't drain DMA write data for devices behind additional PCI-PCI
  bridges underneath the APB PCI-PCI bridge. This workaround (do
  things necessary in order to achieve a manual drain when coherency
  is required) is currently implemented in psycho_setup_intr() and
  psycho_intr_stub() (for easy MFC'ing) and therefore is only applied
  for interrupt handlers. This should be moved to psycho(4)-specific
  bus_dma_tag_create() and bus_dmamap_sync() methods, respectively,
  once this driver is converted to make use of BUS_GET_DMA_TAG(), so
  the workaround is also applied for polling(4) callbacks. [3]
o Fix some minor style issues.

Info from:	OpenSolaris [1]
Info from:	Linux, OpenBSD, OpenSolaris [3]
Suggested by:	Coverity Prevent (CID 682) [2]
MFC after:	1 month
2007-01-08 01:26:47 +00:00
Marius Strobl
114bfbb64e - Improve the comment regarding the workaround for the E250 interrupt map
bug by explaining what the problem is and how the workaround works.
- Fix some cosmetics nits, mainly properly terminate sentences in comments,
  which I missed when backporting the style changes to psycho(4) in psycho.c
  rev. 1.54 due to lack of corresponding code.
- The "USIIe version of the Sabre bridge" actually is termed "Hummingbird";
  name it as such in comments and messages.
2005-12-03 13:08:05 +00:00
Marius Strobl
dcb740a42a Some clean-up, style changes and changes that will reduce differences
between this driver and other Host-PCI bridge drivers based on this one:

- Make the code fit into 80 columns.
- Make the code adhere style(9) (don't use function calls in initializers,
  use uintXX_t instead of u_intXX_t, add missing prototypes, ...).
- Remove unused and superfluous struct declaration, softc member, casts,
  includes, etc.
- Use FBSDID.
- Sprinkle const.
- Try to make comments and messages consistent in style throughout the
  driver.
- Use convenience macros for the number of interrupts and ranges of the
  bridge.
- Use __func__ instead of hardcoded function names in panic strings and
  error messages. Some of the hardcoded function names actually were
  outdated through moving code around. [1]
- Rename softc members related to the PCI side of the bridge to sc_pci_*
  in order to make it clear which side of the bridge they refer to (so
  stuff like sc_bushandle vs. sc_bh is less confusing while reading the
  code).

PR:	76052 [1]
2005-11-22 21:34:26 +00:00
Warner Losh
60727d8b86 /* -> /*- for license, minor formatting changes 2005-01-07 02:29:27 +00:00
Thomas Moestl
2699b91e48 Some code cleanup:
- Fix some comments; remove numerous superfluous or outdated ones.
- Correctly pass on the requesting device when handing requests up
  to the parent bus.
- Use the complete device name, including unit number, to build the
  IOMMU instance name.
- Inline a function that was only used once, and was trivial.
2004-04-25 00:30:28 +00:00
Thomas Moestl
2cda2e47da - Clear the CE AFSR bits which indicate the error condition when handling
a correctable DMA error. Failing to do so can cause the error interrupt
  to be triggered over and over again.
- Clean up the comments for UEAFSR_* constants, fix a typo (UEAFSR_BLK is
  (1 << 23), not (1 << 22)), and add two more. Also, add similar constants
  for the CE AFSR bits.
2003-09-04 15:25:10 +00:00
Thomas Moestl
3a68043d39 - remove some outdated comments
- tweak the announce message a bit
- remove '\n's from a few panic() calls
- don't use the DVMA base adress the firmware reports; instead, figure
  it out from the appropriate register on Sabres and let the IOMMU code
  choose it on Psychos. This also makes the IOMMU TSB size freely
  selectable.
2003-01-06 16:51:06 +00:00
Thomas Moestl
d4523ab223 Fix some comments describing psycho registers.
Approved by:	re
2002-12-01 23:00:41 +00:00
Thomas Moestl
5fb49f9fd6 Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI
code. Both tasks are not always performed completely by the firmware.
The former is required to get some e450 models to boot; the latter fixes
the repeated fifo underruns with hme(4)s and gem(4)s observed on some
machines (and probably performance problems with other peripherals as
well).
2002-06-12 19:20:57 +00:00
Thomas Moestl
4b5504494d Add code to print the fault virtual address for uncorrectable DMA errors
caused by IOMMU misses to aid debugging. This will only work on
UltraSPARC-IIi and IIe.
2002-03-23 20:42:23 +00:00
Thomas Moestl
e37d222c43 Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs).
Use explicit bus space accesses instead of mapping the device memory
into kva.
Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
Thomas Moestl
9d69e46260 Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware
PCI support code, and a driver for the Sun APB PCI-PCI bridge.
Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00