Commit Graph

1271 Commits

Author SHA1 Message Date
Andrew Thompson
a0ba8fd51c Provide a mutex around the read/modify/write of the IXP425_GPIO_*
registers. Giant was used in some places, but not all.
2010-11-14 20:41:22 +00:00
Andrew Thompson
54873b4cd6 Add a GPIO driver for the Gateworks Cambria platform.
The external gpio pins are connected to a PLD on the i2c bus, unfortunatley
this device does not conform by failing to send an ack after each byte written.
The iicbb driver will abort the transfer when the address is not ack'd and it
would introduce a lot of churn to be able to pass a flag down to
iicbb_start/iicbb_write. Instead we do bad things by grabbing the iicbus but
then doing our own bit banging.
2010-11-11 20:18:33 +00:00
Bernd Walter
bfb8239854 add hint for at45d flash device sitting of spibus0 2010-11-11 15:02:14 +00:00
John Baldwin
961135ead8 - Remove <machine/mutex.h>. Most of the headers were empty, and the
contents of the ones that were not empty were stale and unused.
- Now that <machine/mutex.h> no longer exists, there is no need to allow it
  to override various helper macros in <sys/mutex.h>.
- Rename various helper macros for low-level operations on mutexes to live
  in the _mtx_* or __mtx_* namespaces.  While here, change the names to more
  closely match the real API functions they are backing.
- Drop support for including <sys/mutex.h> in assembly source files.

Suggested by:	bde (1, 2)
2010-11-09 20:46:41 +00:00
Rebecca Cran
b1ce21c6ef Fix typos.
PR:	bin/148894
Submitted by:	olgeni
2010-11-09 10:59:09 +00:00
Kevin Lo
d6cb4126e3 Minor cosmetic changes 2010-11-09 09:34:21 +00:00
Kevin Lo
036227ca55 Intel IXP425 SoC is based on the ARMv5TE architecture
MFC after:	3 days
2010-11-08 07:54:24 +00:00
Andrew Thompson
0b773cbb23 Remove line for the uncommitted Cambria gpio drive that snuck in with r214946. 2010-11-07 20:38:14 +00:00
Andrew Thompson
cefd33c787 Hook up the five gpio pins on the Avila board to the gpio framework. There are
actually 16 I/O lines but the other ones are used for system devices and
interrupts.

The IXP4XX platform can set interrupts on these pins for
high/low/rising/falling/transitional but this is not implemented yet.

The Cambria has the same interface but as all the pins are assigned to system
functions the gpio header is toggled via a PLD on the i2c bus and is not
supported by this commit.
2010-11-07 20:33:39 +00:00
John Baldwin
0108cce0a4 Adjust the order of operations in spinlock_enter() and spinlock_exit() to
work properly with single-stepping in a kernel debugger.  Specifically,
these routines have always disabled interrupts before increasing the nesting
count and restored the prior state of interrupts after decreasing the nesting
count to avoid problems with a nested interrupt not disabling interrupts
when acquiring a spin lock.  However, trap interrupts for single-stepping
can still occur even when interrupts are disabled.  Now the saved state of
interrupts is not saved in the thread until after interrupts have been
disabled and the nesting count has been increased.  Similarly, the saved
state from the thread cannot be read once the nesting count has been
decreased to zero.  To fix this, use temporary variables to store interrupt
state and shuffle it between the thread's MD area and the appropriate
registers.

In cooperation with:	bde
MFC after:     1 month
2010-11-05 13:42:58 +00:00
Olivier Houchard
306cc0acfb Try to be a little smart at guessing where _start is located in flash, instead
of relying on a binutils bug.

Reported by:	dim
2010-11-01 21:04:23 +00:00
Alexander Motin
bda55b6adb Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.
2010-10-18 11:30:13 +00:00
Marius Strobl
b56f1ea9d4 Remove a device_printf() accidentally left in r213894.
Submitted by:	jhb
2010-10-15 15:16:36 +00:00
Marius Strobl
d6c65d276e Converted the remainder of the NIC drivers to use the mii_attach()
introduced in r213878 instead of mii_phy_probe(). Unlike r213893 these
are only straight forward conversions though.

Reviewed by:	yongari
2010-10-15 15:00:30 +00:00
Marius Strobl
8e5d93dbb4 Convert the PHY drivers to honor the mii_flags passed down and convert
the NIC drivers as well as the PHY drivers to take advantage of the
mii_attach() introduced in r213878 to get rid of certain hacks. For
the most part these were:
- Artificially limiting miibus_{read,write}reg methods to certain PHY
  addresses; we now let mii_attach() only probe the PHY at the desired
  address(es) instead.
- PHY drivers setting MIIF_* flags based on the NIC driver they hang
  off from, partly even based on grabbing and using the softc of the
  parent; we now pass these flags down from the NIC to the PHY drivers
  via mii_attach(). This got us rid of all such hacks except those of
  brgphy() in combination with bce(4) and bge(4), which is way beyond
  what can be expressed with simple flags.

While at it, I took the opportunity to change the NIC drivers to pass
up the error returned by mii_attach() (previously by mii_phy_probe())
and unify the error message used in this case where and as appropriate
as mii_attach() actually can fail for a number of reasons, not just
because of no PHY(s) being present at the expected address(es).

Reviewed by:	jhb, yongari
2010-10-15 14:52:11 +00:00
Olivier Houchard
41456e2db1 Add the QILA9G20 config files.
Submitted by:	Greg Ansley
2010-10-06 22:41:32 +00:00
Olivier Houchard
d1a346128f Add support for the AT91SAM9260
Submitted by:	Greg Ansley
2010-10-06 22:40:27 +00:00
Olivier Houchard
9195433fdc Add the AT91SAM9G20EK config files.
Submitted by:	Greg Ansley
2010-10-06 22:32:31 +00:00
Olivier Houchard
4ad6106939 if_ate.c:
* Support for sam9 "EMAC" controller.
    * Support for rmii interface to phy.

at91.c & at91sam9.c:

    * Eliminate separate at91sam9.c file.
    * Add new devices to at91sam9_devs table.

at91_machdep.c & at at91sam9_machdep.c:

    * Automatic chip type determination.
    * Remove compile time chip dependencies.
    * Eliminate separate at91sam9_machdep.c file.

at91_pmc.c:

    * Corrected support for all of the sam926? and sam9g20 chips.
    * Remove compile time chip dependencies.

My apologies to Greg for taking so long to take care of it.
2010-10-06 22:25:21 +00:00
Bernd Walter
4a2b4bc031 fix outdated comment 2010-09-28 21:13:54 +00:00
Bernd Walter
974dd68e5c The TWI controller automatically stops if we don't fill up with new data in
time.
2010-09-27 15:58:19 +00:00
Bernd Walter
cd93636f3e fix off by one error for twi reads with len != 1.
STOP must be requested before the last byte is received.
2010-09-27 15:55:30 +00:00
Alexander Motin
cfa892b592 Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's
heatsink termperature in open air from 49C to 43C when idle.
2010-09-18 16:57:05 +00:00
Alexander Motin
afc1cdb92d Clear timer interrupt status before calling callback, not after it,
This fixes timer interrupt losses, fatal in one-shot mode.
2010-09-18 13:44:39 +00:00
Olivier Houchard
68710d7d2f In pmap_remove_all(), do not decrease pm_stats.wired_count if the mapping was
wired, as it's been done later in pmap_nuke_pv().

Submitted by:	Mark Tinguely
2010-09-12 20:46:32 +00:00
Andriy Gapon
3d844eddb7 bus_add_child: change type of order parameter to u_int
This reflects actual type used to store and compare child device orders.
Change is mostly done via a Coccinelle (soon to be devel/coccinelle)
semantic patch.
Verified by LINT+modules kernel builds.

Followup to:	r212213
MFC after:	10 days
2010-09-10 11:19:03 +00:00
Maksim Yevmenkin
93dbfc7840 Add custom kernel configuration and device tree source files for
Seagate FreeAgent DockStar(tm) device. It seems to be a dumb down
version of Marvell SheevaPlug. Device tree source file could use
more tweaking, but at least it wll network boot and run FreeBSD/arm.
2010-09-08 19:50:47 +00:00
Konstantin Belousov
ee235befcb Supply some useful information to the started image using ELF aux vectors.
In particular, provide pagesize and pagesizes array, the canary value
for SSP use, number of host CPUs and osreldate.

Tested by:	marius (sparc64)
MFC after:	1 month
2010-08-17 08:55:45 +00:00
John Baldwin
60c7b36b7a Update various places that store or manipulate CPU masks to use cpumask_t
instead of int or u_int.  Since cpumask_t is currently u_int on all
platforms this should just be a cosmetic change.
2010-08-11 23:22:53 +00:00
John Baldwin
a3870a1826 Very rough first cut at NUMA support for the physical page allocator. For
now it uses a very dumb first-touch allocation policy.  This will change in
the future.
- Each architecture indicates the maximum number of supported memory domains
  via a new VM_NDOMAIN parameter in <machine/vmparam.h>.
- Each cpu now has a PCPU_GET(domain) member to indicate the memory domain
  a CPU belongs to.  Domain values are dense and numbered from 0.
- When a platform supports multiple domains, the default freelist
  (VM_FREELIST_DEFAULT) is split up into N freelists, one for each domain.
  The MD code is required to populate an array of mem_affinity structures.
  Each entry in the array defines a range of memory (start and end) and a
  domain for the range.  Multiple entries may be present for a single
  domain.  The list is terminated by an entry where all fields are zero.
  This array of structures is used to split up phys_avail[] regions that
  fall in VM_FREELIST_DEFAULT into per-domain freelists.
- Each memory domain has a separate lookup-array of freelists that is
  used when fulfulling a physical memory allocation.  Right now the
  per-domain freelists are listed in a round-robin order for each domain.
  In the future a table such as the ACPI SLIT table may be used to order
  the per-domain lookup lists based on the penalty for each memory domain
  relative to a specific domain.  The lookup lists may be examined via a
  new vm.phys.lookup_lists sysctl.
- The first-touch policy is implemented by using PCPU_GET(domain) to
  pick a lookup list when allocating memory.

Reviewed by:	alc
2010-07-27 20:33:50 +00:00
Andrew Turner
fa94061701 Allow external interrupts.
- Set the external pin to interrupt in bus_setup_intr
- Implement bus_config_intr for external interrupts
- Extend arm_{,un}mask_irq to work with external interrupts

Approved by:	imp (mentor)
2010-07-24 23:41:09 +00:00
Andrew Turner
6fc08f19a6 Add the s3c24x0 real time clock driver
Approved by:	imp (mentor)
2010-07-22 23:23:39 +00:00
Andrew Turner
6eae6892da Rework how device memory is allocated on the s3c24x0 CPU's.
The device virtual addresses are now able to be allocated at runtime rather
than from the static pmap_devmap at boot. The only exception is memory
required before we have had a chance to dynamically allocate it.

While here reduce the space between the statically allocated devices by
reducing the distance between the virtual addresses.

Approved by:	imp (mentor)
2010-07-22 23:12:19 +00:00
Alexander Motin
599cf0f197 Fix several un-/signedness bugs of r210290 and r210293. Add one more check. 2010-07-20 15:48:29 +00:00
Alexander Motin
e9f0d5658c Refactor Marvell ARM SoC timer driver to the new timer infrastructure. 2010-07-20 11:46:45 +00:00
Rafal Jaworowski
294e2f046a Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option. 2010-07-19 19:19:33 +00:00
Rafal Jaworowski
4f124b977c Eliminate FDT_IMMR_VA define.
This removes platform dependencies from <machine>/fdt.h for the benfit of
portability.
2010-07-19 18:47:18 +00:00
Rafal Jaworowski
5710b7a9da Move MRVL FDT fixups and PIC decode routine to a platform specific area.
This allows for better encapsulation (and eliminates generic fdt_arm.c, at
least for now).
2010-07-19 18:41:50 +00:00
Olivier Houchard
50a9f1c71c Import preliminary support for Atmel AT91SAM9G20 cpu, and the Hot-e HL201.
This fine work was done by Yohanes Nugroho <yohanes a gmail dot com>
Many thanks to John Nicholls and Thinlinx for providing sample hardware.
2010-07-14 00:48:53 +00:00
Rafal Jaworowski
6031d0b167 Get rid of bootinfo for good in loader (U-Boot-based) and ARM.
For FDT-enabled platforms the device tree is a modern replacement for bootinfo
config data.
2010-07-11 21:11:23 +00:00
John Baldwin
fc0de8f0b6 Move prototypes for kern_sigtimedwait() and kern_sigprocmask() to
<sys/syscallsubr.h> where all other kern_<syscall> prototypes live.
2010-06-30 18:03:42 +00:00
Rafal Jaworowski
915421bba4 Move ARM nexus rman initialization to attach routine.
This fixes a panic, which started to trigger after r209129 cleanup.

Submitted by:	Andrew Turner
2010-06-16 14:10:39 +00:00
Olivier Houchard
8b1f99cdd4 Turn off cache if there's more than one kernel mapping, and one is writable.
Submitted by:   Mark Tinguely
2010-06-15 22:16:02 +00:00
Rafal Jaworowski
98dbf5572a Temporarily bring back the ARM bootinfo (and make tinderbox happy).
BI will be eliminated for good when powerpc transition to FDT is complete.
2010-06-14 16:05:21 +00:00
Rafal Jaworowski
db5ef4fc77 Convert Marvell ARM platforms to FDT convention.
The following systems are involved:

  - DB-88F5182
  - DB-88F5281
  - DB-88F6281
  - DB-78100
  - SheevaPlug

This overhaul covers the following major changes:

  - All integrated peripherals drivers for Marvell ARM SoC, which are
    currently in the FreeBSD source tree are reworked and adjusted so they
    derive config data out of the device tree blob (instead of hard coded /
    tabelarized values).

  - Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
    good by to obio / mbus drivers and numerous hard-coded config data.

Note that world needs to be built WITH_FDT for the affected platforms.

Reviewed by:	imp
Sponsored by:	The FreeBSD Foundation.
2010-06-13 13:28:53 +00:00
Rafal Jaworowski
dc65d002dd Initial FDT infrastructure elements for ARM.
Reviewed by:	imp
Sponsored by:	The FreeBSD Foundation
2010-06-13 13:12:52 +00:00
Rafal Jaworowski
ddf2705d57 Improve style. 2010-06-13 13:08:23 +00:00
Alan Cox
9124d0d6a3 Relax one of the new assertions in pmap_enter() a little. Specifically,
allow pmap_enter() to be performed on an unmanaged page that doesn't have
VPO_BUSY set.  Having VPO_BUSY set really only matters for managed pages.
(See, for example, pmap_remove_write().)
2010-06-11 15:49:39 +00:00
Alan Cox
ce18658792 Reduce the scope of the page queues lock and the number of
PG_REFERENCED changes in vm_pageout_object_deactivate_pages().
Simplify this function's inner loop using TAILQ_FOREACH(), and shorten
some of its overly long lines.  Update a stale comment.

Assert that PG_REFERENCED may be cleared only if the object containing
the page is locked.  Add a comment documenting this.

Assert that a caller to vm_page_requeue() holds the page queues lock,
and assert that the page is on a page queue.

Push down the page queues lock into pmap_ts_referenced() and
pmap_page_exists_quick().  (As of now, there are no longer any pmap
functions that expect to be called with the page queues lock held.)

Neither pmap_ts_referenced() nor pmap_page_exists_quick() should ever
be passed an unmanaged page.  Assert this rather than returning "0"
and "FALSE" respectively.

ARM:

Simplify pmap_page_exists_quick() by switching to TAILQ_FOREACH().

Push down the page queues lock inside of pmap_clearbit(), simplifying
pmap_clear_modify(), pmap_clear_reference(), and pmap_remove_write().
Additionally, this allows for avoiding the acquisition of the page
queues lock in some cases.

PowerPC/AIM:

moea*_page_exits_quick() and moea*_page_wired_mappings() will never be
called before pmap initialization is complete.  Therefore, the check
for moea_initialized can be eliminated.

Push down the page queues lock inside of moea*_clear_bit(),
simplifying moea*_clear_modify() and moea*_clear_reference().

The last parameter to moea*_clear_bit() is never used.  Eliminate it.

PowerPC/BookE:

Simplify mmu_booke_page_exists_quick()'s control flow.

Reviewed by:	kib@
2010-06-10 16:56:35 +00:00
Alan Cox
85a71b2578 Don't set PG_WRITEABLE in pmap_enter() unless the page is managed.
Correct a typo in a nearby comment on sparc64.
2010-06-05 18:20:09 +00:00