process is on the alternate stack or not. For compatibility
with sigstack(2) state is being updated if such is needed.
We now determine whether the process is on the alternate
stack by looking at its stack pointer. This allows a process
to siglongjmp from a signal handler on the alternate stack
to the place of the sigsetjmp on the normal stack. When
maintaining state, this would have invalidated the state
information and causing a subsequent signal to be delivered
on the normal stack instead of the alternate stack.
PR: 22286
-current and RELENG_4 with GENERIC.
NKPT is the number of initial bootstrap page table pages we create for
the kernel during startup. Once VM is up, we resize it as needed, but
with 4G ram, the size of the vm_page_t structures was pushing it over
the limit. The fact that trimmed down kernels boot on 4G ram machines
suggests that we were pretty close to the edge.
The "30" is arbitary, but smaller than the 'nkpt' variable on all
machines that I checked.
- Use a better test for determining when a process is running.
- Convert some checks to assertions.
- Remove unnecessary tests.
- Save the priority before acquiring a mutex rather than in msleep(9).
4) The cardbus CIS code treats the CIS_PTR as a mapping register if
it is mentioned in the CIS. I don't have a spec handy to understand
why the CIS_PTR is mentioned in the CIS, but allocating a memory range
for it is certainly bogus. My patch ignores bar #6 to prevent the
mapping.
[The pccard spec says that BAR 0 and 7 (-1 and 6 in thic case since we
did a minus one) is "reserved". The off by 1 error has been fixed.
also bar=5 is invalid for IO maps, so we check it.]
5) The CIS code allocated duplicate resources to those already found
by cardbus_add_resources(). The fix is to pass in the bar computed
from the CIS instead of the particular resource ID for that bar,
so bus_generic_alloc_resource succeeds in finding the old resource.
[fixed, also removed superfluous (and incorrect) writing back to the
PCI config space.]
7) The CIS code seems to use the wrong bit to determine rather a particular
register mapping is for I/O or memory space. From looking at the
two cards I have, it seems TPL_BAR_REG_AS should be 0x10 instead
of 0x08. Otherwise, all registers that should be I/O mapped gain
a second mapping in memory space.
[Oops, the spec does say 0x10..., fixed]
Submitted by: Justin Gibbs
Providing shell scripts that do nothing but load a similarly named
kernel loadable module in out of vogue.
There is no ibcs2(4) manual page, and I haven't managed to coax
anyone into contributing one based on the linux(4) manual page.
our kernel module system learned how to handle dependencies.
Providing a whole bunch of shell scripts that do nothing but load
a similarly named kernel loadable module is out of vogue.
The svr4(8) manual page has been replaced with a much better svr4(4)
page.
timeout. If DIAGNOSTIC is turned on, then display a message to the console
with a map of which CPUs failed to stop or restart. This gives an SMP box
at least a fighting chance of getting into DDB if one of the other CPUs has
interrupts disabled.
Fix amr_map_command so that 40LD-specific commands get the scatter-gather
list count in the right place. I don't understand why AMI did it like
this, but now the AMI MegaManager can talk to the newer (1600 and later)
controllers.
Remove an unused variable.
Include <machine/clock.h> when necessary.
Tweak some debugging levels to make things more intelligible.
Alter consumers of this method to conform to the new convention.
Minor cosmetic adjustments to bus.h.
This isn't of concern as this interface isn't in use yet.
io or memory space access enabled. This patch defers the setting
of these bits until after all of the mapping registers are probed.
It might be even better to defer this until a particular mapping
is activated and to disable that type of access when a new
register is activated.
2) The PCI spec is very explicit about how mapping registers and
the expansion ROM mapping register should be probed. This patch
makes cardbus_add_map() follow the spec.
3) The PCI spec allows a device to use the same address decoder for
expansion ROM access as is used for memory mapped register access.
This patch carefully enables and disables ROM access along with
resource (de)activiation.
This doesn't include the prefetching detection stuff (maybe later when code is written to actually turn on prefetching). It also does not use the PCI definitions (yet, I'll try to put this in all at once later)
Submitted by: Justin T. Gibbs
- Make pccbb/cardbus kld loadable and unloadable.
- Make pccbb/cardbus use the power interface from pccard instead of inventing its own.
- some other minor fixes
The release engineer keeps using the wrong /boot/cdboot when creating the
ISO images. So we'll add the 4.0-RELEASE cdboot to the tree until someone
bothers to fix the source so a working `cdboot' is built.
1) mpsafe (protect the refcount with a mutex).
2) reduce duplicated code by removing the inlined crdup() from crcopy()
and make crcopy() call crdup().
3) use M_ZERO flag when allocating initial structs instead of calling bzero
after allocation.
4) expand the size of the refcount from a u_short to an u_int, by using
shorts we might have an overflow.
Glanced at by: jake
use a mutex lock when looking up/deleting entries on the hashlist
use a mutex lock on each uidinfo when updating fields
make uifree() a void function rather than 'int' since no one cares
allocate uidinfo structs with the M_ZERO flag and don't explicitly initialize
them
Assisted by: eivind, jhb, jakeb
