Commit Graph

24 Commits

Author SHA1 Message Date
Sam Leffler
0ad2baa062 add IXP4XX_FLASH_SIZE config knob that can be used to override the default
flash size; this is necessary at the moment because we map all of flash at
boot, eventually we'll do this on the fly
2009-03-10 21:49:22 +00:00
Sam Leffler
d212022417 Merge WIP from p4:
o recognize ixp435 cpu
o change memory layout for for ixp4xx to not assume memory is aliases
  to 0x10000000 (Cambria/ixp435 memory starts at zero)
o handle 64 irqs for ixp435
o dual EHCI USB 2.0 controller integral to ixp435
o overhaul NPE code for ixp435 and better MAC+MII naming
o updated NPE firmware (including NPE-A image for ixp435/ixp465)
o Gateworks Cambria board support:
  - IDE compact flash
  - MCU
  - front panel LED on i2c bus
  - Octal LED latch

Sanity-tested with NFS-root on Avila and Cambria boards.  Requires
pending boot2 mods for CF-boot on Cambria.
2008-12-13 01:21:37 +00:00
Stanislav Sedov
b739b60532 - Obtain main clock frequency dynamically based on CKGR_MCFR register
contents.
- It is possible to override the dynamic configuration by using
  AT91C_MAIN_CLOCK option in kernel config.

PR:		arm/128961 (based on)
Submitted by:	Bjorn Konig <bkoenig@alpha-tierchen.de>
Reviewed by:	imp
Approved by:	kib (mentor, implicit)
2008-11-30 22:33:03 +00:00
Rafal Jaworowski
373bbe25ff Introduce basic support for Marvell families of system-on-chip ARM devices:
*  Orion
     - 88F5181
     - 88F5182
     - 88F5281

  * Kirkwood
     - 88F6281

  * Discovery
     - MV78100

The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:

  * GPIO
  * Interrupt controller
  * L1, L2 cache
  * Timers, watchdog, RTC
  * TWSI (I2C)
  * UART

Other peripherals drivers will be introduced separately.

Reviewed by:	imp, marcel, stass (Thanks guys!)
Obtained from:	Marvell, Semihalf
2008-10-13 20:07:13 +00:00
Benno Rice
9722a61504 Support for the XScale PXA255 SoC as found on the Gumstix Basix and Connex
boards.  This is enough to net-boot to multiuser.

Also supported is the SMSC LAN91C111 parts used on the netCF, netDUO and netMMC
add-on boards.

I'll be putting some instructions on how to boot this on the Gumstix boards
online soon.

This is still fairly rough and will be refined over time but I felt it was
better to get this out there where other people can help out.
2008-06-06 05:08:09 +00:00
Kevin Lo
3d2c85cf9a Add CPU_ARM9E 2007-10-31 07:28:45 +00:00
Olivier Houchard
ed0b604f1f Add an option to be able to override the value of the AT91 master clock
frequency. It'd be better to be able to calculate it at runtime, but we need
the information very early, to setup the uart.
2007-10-25 23:02:42 +00:00
Olivier Houchard
128b3d77e8 Add CPU_XSCALE_81342 before I forget again. 2007-06-11 21:31:13 +00:00
Olivier Houchard
f59ae8e84a Add two new options, FLASHADDR, which defines the address the flash is
mapped at, and LOADERRAMADDR, the address at which the loader maps the ram at
at the time the kernel is booted.
They are used to detect if the kernel is booted from the onboard flash.
Define those for the IQ31244
2007-02-19 01:03:08 +00:00
Bernd Walter
ecfa9e8ded MFp4: add BWCT kernel configuration 2007-01-05 02:08:35 +00:00
Sam Leffler
5186f9ffb9 add CPU_XSCALE_IXP425
Reviewed by:	cognet, imp
MFC after:	1 month
2006-11-19 23:56:44 +00:00
Olivier Houchard
11d1528ce0 Finally bring it support for the i80219 XScale processor.
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
2006-08-24 23:51:28 +00:00
Olivier Houchard
49953e11d7 Rewrite ARM_USE_SMALL_ALLOC so that instead of the current behavior, it maps
whole the physical memory, cached, using 1MB section mappings. This reduces
the address space available for user processes a bit, but given the amount of
memory a typical arm machine has, it is not (yet) a big issue.
It then provides a uma_small_alloc() that works as it does for architectures
which have a direct mapping.
2006-08-08 20:59:38 +00:00
Warner Losh
cbc25facdf For the moment, make board configuration a compile time option. This
saves space in the final kernel, but at the expense of flexibility to
boot the same kernel accross a family of boards.
2006-07-14 21:59:54 +00:00
Olivier Houchard
d661dc8070 Convert the last offender, the SA1110 port, to ARM32_NEW_VM_LAYOUT, and
completely nuke the !ARM32_NEW_VM_LAYOUT case.
2006-06-06 21:06:57 +00:00
Olivier Houchard
f14c3a8aac Make VERBOSE_INIT_ARM compile by fixing various printf formats, and add it
as an option.

Submitted by:   Max N. Boyarov <m.boyarov at bsd dot by>
2006-06-06 01:14:12 +00:00
Olivier Houchard
d5d776c16b Resurrect Skyeye support :
Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds
workarounds for things skyeye doesn't simulate. Specifically :
- Use USART0 instead of DBGU as the console, make it not use DMA, and           manually provoke an interrupt when we're done in the transmit function.
- Skyeye maintains an internal counter for clock, but apparently there's
no way to access it, so hack the timecounter code to return a value which
is increased at every clock interrupts. This is gross, but I didn't find a
better way to implement timecounters without hacking Skyeye to get the
counter value.
- Force the write-back of PTEs once we're done writing them, even if they
are supposed to be write-through. I don't know why I have to do that.
2006-05-13 23:41:16 +00:00
Olivier Houchard
1ac232117c Add a new option, XSCALE_DISABLE_CCNT, to not use the xscale ccnt as a
timecounter (because gxemul doesn't emule it yet).
2006-04-06 17:11:08 +00:00
Olivier Houchard
527962c8c7 The IQ80321 clock is 200MHz, but the IQ80321 is 198MHz, so add a kernel option
to override the frequency
2005-12-09 23:52:51 +00:00
Olivier Houchard
7ab3afdd5e Add ARM_USE_SMALL_ALLOC. 2005-06-07 23:05:04 +00:00
Olivier Houchard
4b2c5061c2 Add a new option, ARM_CACHE_LOCK_ENABLE (I forgot it in my last commit). 2005-02-26 22:41:07 +00:00
Olivier Houchard
c6cc6da44f Add a new option, ARM32_NEW_VM_LAYOUT. When set, we try to put up to 4
L2 tables in one page, instead of the old 1 L2 table <=> 1 page behavior.
While I'm there, add ARM9_CACHE_WRITE_THROUGH, which I forgot last time.
2004-11-10 22:08:27 +00:00
Olivier Houchard
c2f29b3e64 Add new options :
PHYSADDR : Address of the physical memory
KERNPHYSADDR : Physical address where the kernel starts
KERNVIRTADDR : Virtual address of the kernel
STARTUP_PAGETABLE_ADDR : Where to put the page table at bootstrap
+ Xscale specific options
2004-09-23 22:52:25 +00:00
Olivier Houchard
78b36e3ca5 Add config magic for arm. 2004-05-14 11:49:40 +00:00