Commit Graph

7 Commits

Author SHA1 Message Date
Mark Johnston
918988576c Avoid relying on header pollution from sys/refcount.h.
MFC after:	3 days
Sponsored by:	The FreeBSD Foundation
2019-07-29 20:26:01 +00:00
Landon J. Fuller
be9a13138e bhnd(4): Use the new BHND_CAP_BP64 capability flag to exclude DMA
translations unsupported by the backplane.
2018-03-29 19:48:50 +00:00
Landon J. Fuller
566ca880a1 bhnd(4): Include board_devid in the bhnd_board_info structure, and populate
the expected default board_vendor value on MIPS SoCs.

This is required by bwn(4) to differentiate between single-band and
dual-band device variants that otherwise share a common chip ID.

Approved by:	adrian (mentor, implicit)
Sponsored by:	The FreeBSD Foundation
2017-12-14 01:58:05 +00:00
Landon J. Fuller
9ed453245b bhnd(4): Add support for querying DMA address translation parameters
BHND Wi-Fi chipsets and SoCs share a common DMA engine, operating within
backplane address space. To support host DMA on Wi-Fi chipsets, the bridge
core maps host address space onto the backplane; any host addresses must
be translated to their corresponding backplane address.


- Defines a new bhnd_get_dma_translation(9) API to support querying DMA
  address translation parameters from the bhnd(4) bus.
- Extends bhndb(4) to provide DMA translation descriptors from a DMA
  address translation table defined in the host bridge-specific
  bhndb_hwcfg.
- Defines bhndb(4) DMA address translation tables for all supported host
  bridge cores.
- Extends mips/broadcom's bhnd_nexus driver to return an identity (no-op)
  DMA translation descriptor; no translation is required when addressing
  the SoC backplane.

Approved by:	adrian (mentor)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12582
2017-11-21 23:25:22 +00:00
Landon J. Fuller
caeff9a3c2 bhnd(4): implement MIPS and PCI(e) interrupt support
On BHND MIPS SoCs, this replaces the use of hard-coded MIPS IRQ#s in the
common bhnd(4) core drivers; we now register an INTRNG child PIC that
handles routing of backplane interrupt vectors via the MIPS core.

On BHND PCI devices, backplane interrupt vectors are now routed to the
PCI/PCIe host bridge core when bus_setup_intr() is called, where they are
dispatched by the PCI core via a host interrupt (e.g. INTx/MSI).

The bhndb(4) bridge driver tracks registered interrupt handlers for the
bridged bhnd(4) devices and manages backplane interrupt routing, while
delegating actual bus interrupt setup/teardown to the parent bus on behalf
of the bridged cores.

Approved by:	adrian (mentor, implicit)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12518
2017-11-21 23:15:20 +00:00
Landon J. Fuller
8e35bf8319 bhnd: Implement bhnd(4) platform device registration.
Add bhnd(4) API for explicitly registering BHND platform devices (ChipCommon,
PMU, NVRAM, etc) with the bus, rather than walking the newbus hierarchy to
discover platform devices. These devices are now also refcounted; attempting
to deregister an actively used platform device will return EBUSY.

This resolves a lock ordering incompatibility with bwn(4)'s firmware loading
threads; previously it was necessary to acquire Giant to protect newbus access
when locating and querying the NVRAM device.

Approved by:	adrian (mentor)
Sponsored by:	The FreeBSD Foundation
Differential Revision:	https://reviews.freebsd.org/D12392
2017-09-27 19:44:23 +00:00
Landon J. Fuller
8f3bba2d35 [mips/broadcom] Move MIPS-specific bhnd(4) nexus drivers to
sys/mips/broadcom, and add MIPS/BCM4706-specific workaround to
bhnd_nexus_is_hw_disabled() -- the BCM4706 low-cost package leaves
secondary GMAC cores floating.

Reviewed by:	mizhka
Approved by:	adrian (mentor)
Differential Revision:	https://reviews.freebsd.org/D9499
2017-02-13 19:58:55 +00:00