Commit Graph

24 Commits

Author SHA1 Message Date
John Baldwin
98f9879242 Introduce a standard name for the lock protecting an interrupt controller
and it's associated state variables: icu_lock with the name "icu".  This
renames the imen_mtx for x86 SMP, but also uses the lock to protect
access to the 8259 PIC on x86 UP.  This also adds an appropriate lock to
the various Alpha chipsets which fixes problems with Alpha SMP machines
dropping interrupts with an SMP kernel.
2001-12-20 23:48:31 +00:00
Jonathan Lemon
9497337452 The DEC kn300 has special code for console handling hardcoded here, so add
a call to promcndetach() to explicitly turn off the prom console.

Tested by: Jeff Roberson
2001-11-22 02:41:34 +00:00
Matt Jacob
f43f61207d Fix misspelling in comment. 2001-10-31 18:07:38 +00:00
John Baldwin
e37d2a8c82 Remove unneeded sys/mutex.h includes. 2001-10-19 19:23:32 +00:00
Andrew Gallatin
29e7f33db5 fix alpha-MD compile errors after the vm_mtx commit 2001-05-20 16:22:46 +00:00
Matt Jacob
888620f24e Doug found that doing a W1C on MCPCIA_INT_REQ just around the time you
clear MCPCIA_INT_MASK0 helps things substantially. So, why not indeed?

Rearrange irq and cookie calculation to use shifts/masks instead
of division. Fix things to correctly remember the intpin for that
one in a million non-INTA PCI device.
2001-02-13 22:48:12 +00:00
Matt Jacob
d2a4644848 add defines for EISA, NCR IRQs; add defines for MID and SLOT shift values 2001-02-13 22:46:30 +00:00
Matt Jacob
e3981f1a78 add mcbus minimum id value 2001-02-13 22:45:53 +00:00
Matt Jacob
fcd34891a6 Doug noticed that the bit values for _MCPCIA_INT_ACK0/_MCPCIA_INT_ACK1
made no sense in the context of wrapping them within the _SYBRIDGE macro-
or anything like it- so we concluded that this must have been a typo
in the docs.  This also doesn't use the same bridge offset as anything
else.

Add some defines for the INT_CTL register.
2001-02-13 22:44:21 +00:00
John Baldwin
522be16a94 Use the MI ithread helper functions in the alpha hardware interrupt code. 2001-02-09 17:53:23 +00:00
Matt Jacob
38e147e106 Fix ypo in essage about isabling EISA nterrupt ector
(tip 'o the tired cap to Bernd Walter <ticso@cicely5.cicely.de>)
2000-12-15 23:09:05 +00:00
Matt Jacob
6cd8749dbf Add route interrupt method. 2000-12-13 09:07:16 +00:00
Matt Jacob
bd1c746647 Comment out debug printfs about enable/disable ints.
Current now appears to work at least fitfully on one Rawhide.
2000-12-04 01:33:44 +00:00
Matt Jacob
328b7df026 Clean this is up a bit for multiple MIDs... We can figure out which MID
for an interrupt to enable/disable from the vector (and GID too, if we
had multiple GIDs)- so, stupidly for now, search for the right mcpcia's
softc so we have the right base address for the bridge CSR to apply
IRQ bit-twiddle's to. Alas- this doesn't yet allow us to run, but it's
the right direction.
2000-11-08 18:48:21 +00:00
John Baldwin
a07b7a4e35 Pass in the new-bus flags to alpha_setup_intr(). 2000-11-01 18:40:42 +00:00
John Baldwin
1931cf940a - Heavyweight interrupt threads on the alpha for device I/O interrupts.
- Make softinterrupts (SWI's) almost completely MI, and divorce them
  completely from the x86 hardware interrupt code.
  - The ihandlers array is now gone.  Instead, there is a MI shandlers array
    that just contains SWI handlers.
  - Most of the former machine/ipl.h files have moved to a new sys/ipl.h.
- Stub out all the spl*() functions on all architectures.

Submitted by:	dfr
2000-10-05 23:09:57 +00:00
Doug Rabson
21c3015a24 * Completely rewrite the alpha busspace to hide the implementation from
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
  which call busspace.
* Rework pci config accesses to route through the pcib device instead of
  calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Matt Jacob
e8ad1d0707 Handle (for now) trivial one level bridge case so we can get the
slot that the bridge happens to be in so we get interrupts working
on bridged cards.
2000-07-13 03:45:11 +00:00
Matt Jacob
aa5904a62a Coordinate with change to mcpcia_pci.c- major primary busses on each
hose are 16 PCI instances apart. This allows us to recognize secondary
PCI busses (at least to a first level) until the pci infrastructure is
fixed.

Turn on support for secondary cycles, too.  Redo debug printouts.
2000-07-10 00:34:18 +00:00
Doug Rabson
e3227bc7a6 Enable EISA interrupts if the mcpcia has an attached EISA bus. 2000-05-13 21:33:57 +00:00
Matt Jacob
f66ed5ddfa Change references/comments about 'secondary' to reflect that while we'd
like to see the true SRM bus number be passed to us, instead, we get FreeBSD's
PCI bus instance number (Brzzt! Wrong Answer!).

Also, once we've seen the MCPCIA that has the EISA bus on it, call
dec_kn300_cons_init just before configuring devices on this bus.
2000-05-09 02:20:44 +00:00
Matt Jacob
157ffa95ef Pass the vector on thru instead of checking EISA/ISA ints. It turns
out the FreeBSD code did the right thing by starting EISA/ISA vectors
at 0x800.
2000-05-07 05:49:27 +00:00
Matt Jacob
d55ab6af0d EISA/ISA memory space is any pa < 8MB. 2000-05-07 05:31:39 +00:00
Matt Jacob
34255ec554 Add in a first pass at Alpha 4100 (Rawhide) support. It doesn't quite
boot all the way yet, but it's darn close (blows up somewhere probing
the PS/2 mouse on the EISA bus).
2000-05-07 04:53:04 +00:00