It seems the EEE made RX MAC enter LPI(Low Power Idle) mode such
that dwc(4) was not able to receive packets. Ideally dwc(4) should
be able to use EEE to save power during periods of low link
utilization(i.e. gating off clock). Due to lack of dwc(4)
datasheet it's not easy to take required steps for EEE on LPI
enter/exit events. Disabling EEE in PHY seems to be easy
workaround until dwc(4) supports EEE.
Updating EEE advertisement register on RTL8211F seems to have no
effect until reprogramming MII_ANAR, MII_100T2CR and MII_BMCR
with auto-negotiation. It's not clear whether it's related with
mii_phy_reset()'s BMCR_ISO handling for RTL8211F though.
It seems rgephy_reset() needs careful investigation for newer
RealTek PHYs.
Ganbold submitted working version based on NetBSD change and
tested lots of changes I made. Thanks a lot!
Submitted by: ganbold (initial version)
In collaboration with: ganbold
auto-correction. This change makes re(4) establish a link with
a system using non-crossover UTP cable.
Tested by: Michael BlackHeart < amdmiek <> gmail dot com >
made by Michael Eisele and the patch was slightly modified by me.
With this change several NVIDIA ethernet controllers(e.g. MCP61)
works.
RTL8211B(L) is RealTek's new gigabit PHY. The PHY has several
features including crossover correction, polarity correction as
well as supporting triple speed(10/100/1000bps). Data transfer
between MAC and PHY is via RGMII for 1000baseT, MII for
10baseT/100baseTX.
Unfortunately, RealTek used the same model number for RTL8211B(L)
PHY so there is no way to discriminate between RTL8211B(L) and its
predecessors. ATM RTL8211B uses revision number 2 so checking the
revision number seems to be only way to identify it.
Obtained from: Michael Eisele [1]
Tested by: clemens fischer < ino-qc AT spotteswoode DOT de DOT eu DOT org >
ethernet chips. This driver is pretty simple, however it contains
special DSP initialization code which is needed in order to get
the chip to negotiate a gigE link. (This special initialization
may not be needed in subsequent chip revs.) Also:
- Fix typo in if_rlreg.h (RL_GMEDIASTAT_1000MPS -> RL_GMEDIASTAT_1000MBPS)
- Deal with shared interrupts in re_intr(): if interface isn't up,
return.
- Fix another bug in re_gmii_writereg() (properly apply data field mask)
- Allow PHY driver to read the RL_GMEDIASTAT register via the
re_gmii_readreg() register (this is register needed to determine
real time link/media status).
