Commit Graph

43 Commits

Author SHA1 Message Date
Attilio Rao
590f9303e5 Merge from vmobj-rwlock branch:
Remove unused inclusion of vm/vm_pager.h and vm/vnode_pager.h.

Sponsored by:	EMC / Isilon storage division
Tested by:	pho
Reviewed by:	alc
2013-02-26 01:00:11 +00:00
Juli Mallett
312af517e3 Remove platform APIs which are not used by any code and which had only stub
implementations or no implementation on all platforms.

Some of these functions might be good ideas, but their semantics were unclear
given the lack of implementation, and an unlucky porter could be fooled into
trying to implement them or, worse, being baffled when something like
platform_trap_enter() failed to be called.
2012-03-12 07:34:15 +00:00
Juli Mallett
723616952d At the risk of reducing source compatibility with old NetBSD and Sprite:
o) Get rid of some unused macros related to features we don't intend to
   provide.
o) Get rid of macro definitions for MIPS-I CPUs.  We are not likely to
   support anything that predartes MIPS-III.
o) Respell MIPS3_* macros as MIPS_*, which is how most of them were being
   used already.
o) Eliminate a duplicate and mostly-unused set of exception vector macros.

There's still considerable duplication and lots more obsolete in our headers,
but this reduces one of the larger files to a size where one could reckon
about the correctness of its contents with a mere few hours of contemplation.

There is, of course, a question of whether we need definitions for fields,
registers and configurations that we are unlikely to ever use or implement,
even if they're not obsolete since 1991.  FreeBSD is not a processor
reference manual, and things that aren't used may be wrong, or may be
duplicated because nobody could possibly actually know whether they're
already defined.
2012-03-06 19:01:32 +00:00
Kevin Lo
281f0ca8e7 Remove duplicate header includes 2011-06-26 10:07:48 +00:00
Attilio Rao
f89d6b3f06 Fix a brain-o in platform_cpu_mask() by just specifying a possible
cpuset_t to be copied, rather than return the array.
I can't rely anymore on this being a simple int/long object.

Reported by:	art
2011-05-13 19:56:58 +00:00
Attilio Rao
245a253538 Add the cpuset_t conversion for mips. 2011-05-13 16:42:05 +00:00
Rebecca Cran
6bccea7c2b Fix typos - remove duplicate "the".
PR:	bin/154928
Submitted by:	Eitan Adler <lists at eitanadler.com>
MFC after: 	3 days
2011-02-21 09:01:34 +00:00
Juli Mallett
1591f3f18c Allow the platform code to return a bitmask of running cores rather than just
a number of cores, this allows for a sparse set of CPUs.  Implement support
for sparse core masks on Octeon.

XXX jeff@ suggests that all_cpus should include cores that are offline or
    running other applications/OSes, so the platform API should be further
    extended to allow us to set all_cpus to include all cores that are
    physically-present as opposed to only those that are running FreeBSD.

Submitted by:	Bhanu Prakash (with modifications)
Reviewed by:	jchandra
Glanced at by:	kib, jeff, jhb
2011-02-12 02:08:24 +00:00
Oleksandr Tymoshenko
bd01e50ca0 - dump_avail layout should be sequence of [start, end)
pairs, not <start, size>.

Spotted by: alc@
2010-12-09 07:47:40 +00:00
Oleksandr Tymoshenko
99629fa36d - Populate dump_avail with proper values from phys_avail 2010-12-09 07:01:03 +00:00
Warner Losh
161b83b959 Remove the 'machine mips' from DEFAULTS. Put the proper 'machine mips
mipsel' or 'machine mips mipseb' into the config file (with a few 64's
tossed in for good measure).  This will let us build the proper
kernels with different worlds as part of make universe.
2010-11-13 22:34:12 +00:00
Neel Natu
5df4b6be91 Enforce that 'pmap_kenter()' is only used to establish cacheable mappings.
Mappings with other cacheability attributes can be established, if needed,
by using 'pmap_kenter_attr()'.

Suggested by:	jchandra, imp
2010-09-22 02:26:07 +00:00
Neel Natu
885b75a559 Make the meaning of the 'mask' argument to 'set_intr_mask(mask)' consistent
with the meaning of IM bits in the status register.

Reviewed by:	jmallett, jchandra
2010-09-15 05:10:50 +00:00
Andriy Gapon
3d844eddb7 bus_add_child: change type of order parameter to u_int
This reflects actual type used to store and compare child device orders.
Change is mostly done via a Coccinelle (soon to be devel/coccinelle)
semantic patch.
Verified by LINT+modules kernel builds.

Followup to:	r212213
MFC after:	10 days
2010-09-10 11:19:03 +00:00
Neel Natu
3ca4a6cdd3 Remove redundant declaration of 'pcib_driver' class from sb_zbpci.c. This
causes a compilation error.

The declaration is provided by sys/dev/pci/pcib_private.h starting from r210864.
2010-08-06 07:03:22 +00:00
Neel Natu
d3c1485e8f Use a signed integer to hold the address of a register.
This does the right thing by sign extending the address when compiling for
the n64 abi.
2010-08-06 05:30:55 +00:00
Neel Natu
482287c6af uint64_t is 'unsigned long' in n64 build, so compiler is unhappy if the
format specifier in printf is "%llu".

Use "%ju" instead.
2010-08-06 05:24:41 +00:00
Neel Natu
f49fde7faf Fix a race between clock_intr() and tick_ticker() when updating
'counter_upper' and 'counter_lower_last'. The race exists because
interrupts are enabled even though tick_ticker() executes in a
critical section.

Fix a bug in clock_intr() in how it updates the cached values of
'counter_upper' and 'counter_lower_last'. They are updated only
when the COUNT register rolls over. More interestingly it will *never*
update the cached values if 'counter_lower_last' happens to be zero.

Get rid of superfluous critical section in clock_intr(). There is no
reason to do this because clock_intr() executes in hard interrupt
context.

Switch back to using 'tick_ticker()' as the cpu ticker for Sibyte.

Reviewed by:	jmallett, mav
2010-08-05 04:59:54 +00:00
Warner Losh
d3dbb44345 Remove redunant machine/cpuregs.h include.
Also, spell things like in machine/cpuregs.h instead of machine/cpu.h.
2010-07-13 22:30:27 +00:00
Neel Natu
c0fd703892 Fix Sibyte SMP kernel breakage caused by r208249.
We need to include the header file that provides declaration of the
smp_topo_none() function.
2010-05-18 05:12:54 +00:00
Randall Stewart
bc198428ea Adds JC's cleanup patches that fix it so
we call an platform dependant topo function as
well as clean up all the XLR specific ifdefs around
smp platform init.

Obtained from:	JC
2010-05-18 04:02:34 +00:00
Juli Mallett
38f836dbb3 o) Remove default MAXMEM on SWARM; pmap can readily use lmem for >512M
physical addresses.
o) Set a local maxmem in sb_machdep.c to avoid trying to use pages over 2^64
   under 32-bit ABIs.  Our pmap needs corrected to use vm_paddr_t consistently,
   then we can make vm_paddr_t 64-bit under 32-bit ABIs and add code in pmap
   to limit phys_avail by the maximum PFN that a 32-bit PTE can hold.
2010-04-23 19:20:56 +00:00
Neel Natu
bfd506a024 Replace sb_store64()/sb_load64() with mips3_sd()/mips3_ld() respectively.
Obtained from NetBSD.

Suggested by: jmallett@
2010-03-26 07:15:27 +00:00
Neel Natu
69a5a0bfea Sibyte provides a 64-bit read-only counter that counts at half the processor
frequency. This counter can be accessed coherently from both cores.

Use this as the preferred timecounter for the SWARM kernels.

The CP0 COUNT register is unusable as the timecounter on SMP platforms because
the COUNT registers on different CPUs are not guaranteed to be in sync.
2010-03-20 05:49:06 +00:00
Neel Natu
293f20dffb Make sure that the registers 'v0' and 'v1' are properly sign-extended
when sb_load64() returns.

Some 32-bit arithmetic operations (e.g. subu) have unpredicatable results
when operating on 64-bit registers that are not properly sign-extended.
2010-03-20 05:21:14 +00:00
Neel Natu
6be470c077 Add support for CPUs with cache coherent DMA. The two main changes are:
- We don't need to fall back to uncacheable memory to satisfy BUS_DMA_COHERENT
  requests on these CPUs.

- The bus_dmamap_sync() is a no-op for these CPUs.

A side-effect of this change is rename DMAMAP_COHERENT flag to
DMAMAP_UNCACHEABLE. This conveys the purpose of the flag more accurately.

Reviewed by: gonzo, imp
2010-03-04 05:23:08 +00:00
Neel Natu
f7bb996d92 Various fixes to get the SWARM config working on a big-endian Sibyte CPU.
Getting the little-endian PCI bus working on the big-endian CPU proved to be
quite challenging. We let the PCI devices be mapped in the "match byte lanes"
address window. This is where they are mapped by the CFE and DMA transfers
generated to or from addresses within this window are not subject to automatic
byte-swapping.

However any access by the driver to memory-mapped pci space is redirected
via the "match bit lanes" address window. We get the benefit of automatic
byte swapping through this address window and drivers don't need to change
to deal with CPU big-endianness.
2010-02-17 06:43:37 +00:00
Neel Natu
9dcae110dc Remove the PCI_IOSPACE_SIZE and PCI_IOSPACE_ADDR hack from nexus.c. Implement
this in the Sibyte PCI hostbridge driver instead.

The nexus driver sees resource allocation requests for memory and irq
resources only. These are legitimate resources on all MIPS platforms.

Suggested by: imp
2010-02-12 02:59:49 +00:00
Neel Natu
1d4fd9f5a8 SMP support for the mips port.
The platform that supports SMP currently is a SWARM with a dual-core Sibyte
processor. The kernel config file to use is SWARM_SMP.

Reviewed by: imp, rrs
2010-02-09 06:24:43 +00:00
Neel Natu
d3e24a4579 Initialize interrupt controller early on. 2010-02-05 03:22:04 +00:00
Neel Natu
c3f7e882dc Reimplement all functions to access the system control unit in C.
The only reason we need to have the sb_load64() and sb_store64()
functions in assembly is to cheat the compiler and generate the
'ld' and 'sd' instructions which it otherwise will not do when
compiling for a 32-bit architecture. There are some 64-bit
registers in the SCD unit that must be accessed using 64-bit
load and store instructions.
2010-02-05 03:20:47 +00:00
Neel Natu
c8f4860360 style: don't need to use braces for single line control statements. 2010-02-05 02:40:42 +00:00
Neel Natu
d87b96dd84 Install the XTLB exception handler for Sibyte processors.
This is a workaround for the fact that the CFE is compiled as a 64-bit
application and therefore sets the SR_KX bit every time we call into
it (for e.g. console).

A TLB miss for any address above 0xc0000000 with the SR_KX bit set will
end up at the XTLB exception vector. We workaround this by copying the
standard TLB handler at the XTLB exception vector.

Approved by: imp (mentor)
2010-01-26 03:39:10 +00:00
Oleksandr Tymoshenko
d86043b594 - Call post-boot fixup function in order to get proper static
symbols resolving in DDB
- When zeroing .bss/.sbss do not round end address to page boundary,
    it's not neccessary and might destroy data pased by trampoline or
    boot loader
2010-01-25 00:44:05 +00:00
Neel Natu
531c6502cc Remove Sibyte specific code from locore.S that sets the k0seg coherency.
Move it to platform_start() instead.

Approved by: imp (mentor)
2010-01-23 03:19:13 +00:00
Warner Losh
0287b24426 Remove redundant interrupt mapper code. We don't need to disable the
interrupt sources feeding into a hardintr anymore. The
mips_mask_hard_irq() function does that for us while an interrupt is
being processed.

Submitted by:	neel@
2010-01-11 17:14:46 +00:00
Warner Losh
474dfef751 Get sb_zbpci.c compiling again after the macros PCI_BUSMAX,
PCI_SLOTMAX and PCI_FUNCMAX were moved to pcireg.h.

Submitted by:	neel@
2010-01-11 17:14:10 +00:00
Warner Losh
3ad9e328b8 Rename mips_pcpu_init to mips_pcpu0_init since it applies only to the
BSP.  Provide a missing prototype.
2010-01-09 03:08:22 +00:00
Warner Losh
a096e4b36b Centralize initialization of pcpu, and set curthread early... 2010-01-08 22:48:21 +00:00
Neel Natu
64b53d19bd Remove all CFE-specific code from locore.S. The CFE entrypoint initialization
is now done in platform-specific code.

Approved by: imp (mentor)
2010-01-06 06:42:08 +00:00
Randall Stewart
8fae280afb With this commit our friend RMI will now compile. I have
not tested it and the chances of it running yet are about
ZERO.. but it will now compile. The hard part now begins,
 making it run ;-)
2009-10-30 08:53:11 +00:00
Randall Stewart
3f907e3338 Does 4 things:
1) Adds future RMI directories
2) Places intr_machdep.c in specfic files.arch pointing to the generic
   intr_machdep.c.  This allows us to have an architecture dependant intr_machdep.c
   (which we will need for RMI) in the machine specific directory
3) removes intr_machdep.c from files.mips
4) Adds some TARGET_XLR_XLS ifdef's for the machine specific intra_machdep.h. We
   may need to look at finding a better place to put this. But first I want to
   get this thing compiling.
2009-10-15 21:03:32 +00:00
Warner Losh
f94784e818 Add sibyte device support.
Submitted by:	Neelkanth Natu
2009-07-04 03:05:48 +00:00