Commit Graph

39 Commits

Author SHA1 Message Date
Maxime Henrion
141bacb048 Change the operation parameter of bus_dmamap_sync() from an
enum to an int and redefine the BUS_DMASYNC_* constants as
flags.  This allows us to specify several operations in one
call to bus_dmamap_sync() as in NetBSD.
2003-04-10 23:03:33 +00:00
Jake Burkholder
58d7ebfa7c Use vm_paddr_t for physical addresses. 2003-04-08 06:35:09 +00:00
Jake Burkholder
868aaa93bc Set the cache line size for subordinate pci bridges as well as for their
child devices.  This fixes dma timeouts for devices behind the bridge.

Reported by:	simokawa
Tested by:	simokawa
2003-03-27 02:01:59 +00:00
Warner Losh
a163d034fa Back out M_* changes, per decision of the TRB.
Approved by: trb
2003-02-19 05:47:46 +00:00
Scott Long
c07f24ca0c Fix some more missing dt_ prefixes for dma tag fields. 2003-01-29 17:41:29 +00:00
Scott Long
5193a34646 Implement bus_dmamem_alloc_size() and bus_dmamem_free_size() as
counterparts to bus_dmamem_alloc() and bus_dmamem_free().  This allows
the caller to specify the size of the allocation instead of it defaulting
to the max_size field of the busdma tag.

This is intended to aid in converting drivers to busdma.  Lots of
hardware cannot understand scatter/gather lists, which forces the
driver to copy the i/o buffers to a single contiguous region
before sending it to the hardware.  Without these new methods, this
would require a new busdma tag for each operation, or a complex
internal allocator/cache for each driver.

Allocations greater than PAGE_SIZE are rounded up to the next
PAGE_SIZE by contigmalloc(), so this is not suitable for multiple
static allocations that would be better served by a single
fixed-length subdivided allocation.

Reviewed by:	jake (sparc64)
2003-01-29 07:25:27 +00:00
Alfred Perlstein
44956c9863 Remove M_TRYWAIT/M_WAITOK/M_WAIT. Callers should use 0.
Merge M_NOWAIT/M_DONTWAIT into a single flag M_NOWAIT.
2003-01-21 08:56:16 +00:00
Thomas Moestl
fe461235a2 Change the iommu code to be able to handle more than one DVMA area per
map. Use this new feature to implement iommu_dvmamap_load_mbuf() and
iommu_dvmamap_load_uio() functions in terms of a new helper function,
iommu_dvmamap_load_buffer(). Reimplement the iommu_dvmamap_load()
to use it, too.
This requires some changes to the map format; in addition to that,
remove unused or redundant members.
Add SBus and Psycho wrappers for the new functions, and make them
available through the respective DMA tags.
2003-01-06 21:59:54 +00:00
Thomas Moestl
08707f05a0 Prefix the members of struct bus_space_tag and struct bus_dma_tag with
a uniqifier. No functional changes.
2003-01-06 19:43:10 +00:00
Thomas Moestl
8286df3339 Initialize the cache line size register of all PCI devices in the
initial setup pass.
2003-01-06 17:12:23 +00:00
Thomas Moestl
3a68043d39 - remove some outdated comments
- tweak the announce message a bit
- remove '\n's from a few panic() calls
- don't use the DVMA base adress the firmware reports; instead, figure
  it out from the appropriate register on Sabres and let the IOMMU code
  choose it on Psychos. This also makes the IOMMU TSB size freely
  selectable.
2003-01-06 16:51:06 +00:00
Jens Schweikhardt
d64ada501a Fix typos, mostly s/ an / a / where appropriate and a few s/an/and/
Add FreeBSD Id tag where missing.
2002-12-30 21:18:15 +00:00
Thomas Moestl
a9dace022e Exclude yet more interrupt mapping registers from the OBIO INO search,
namely the ones for the timers, error handling and power management.
The registers for the timers, power management and PCI bus b errors are
reserved on Sabres (US-IIi) and can lead to false matches there.
Since all of them are never used for devices on the bus, they can be omitted
safely.

Approved by:	re
2002-12-06 13:16:52 +00:00
Thomas Moestl
f57d04ab1d Always initialize the UPA target module id in the interrupt mapping
register to the one of the processor doing the interrupt setup. This
is required since this field is preinitialized to 0, but there exist
machines which have no processor with a MID of 0 (e.g. e450s with 1 or 2
processors).

Add some more macros for handle the interrupt mapping registers, and
rename some existing ones for consistency.

Approved by:	re
2002-12-01 23:30:26 +00:00
Thomas Moestl
0aa267f6a7 1.) Do not look for PCI INOs in the FFB interrupt mapping registers; they
are nevers used for PCI interrupts, but can cause false matches since
    they are fully programmable.
2.) Skip the mapping registers for slot a2 and a3 on "psycho" bridges,
    since they are not present there. Again, this could cause false matches,
    which would result in the interrupt being delivered at most once.

Submitted by:	jake (2)
Approved by:	re
2002-12-01 23:21:15 +00:00
Thomas Moestl
ed2f312db5 Reverse the quirk table entry for swizzling on a missing interrupt map;
this is now done on all machines except for some known problematic ones.

Add an additional guard to make sure that the interrupt numbers are
in the correct range before swizzling. This should catch any remaining
models for which the swizzle is inappropriate.

Correct the swizzle calculation to account for the fact that the parent
interrupt numbers to be swizzled are 1-based.

Approved by:	re
2002-12-01 23:06:14 +00:00
Thomas Moestl
d4523ab223 Fix some comments describing psycho registers.
Approved by:	re
2002-12-01 23:00:41 +00:00
Thomas Moestl
222e92877c Don't register the powerfail interrupt as fast in the
non-DEBUGGER_ON_POWERFAIL case so that shutdown_nice() can be called
without problems.

Reported & tested by:	Gavin Atkinson <gavin@ury.york.ac.uk>
2002-11-14 11:29:16 +00:00
Thomas Moestl
8c8a1169df Add two new workaround for firmware anomalies:
1. At least some Netra t1 models have PCI buses with no associated
   interrupt map, but obviously expect the PCI swizzle to be done with
   the interrupt number from the higher level as intpin. In this case,
   the mapping also needs to continue at parent bus nodes.
   To handle that, add a quirk table based on the "name" property of
   the root node to avoid breaking other boxen. This property is now
   retrieved and printed at boot.
2. On SPARCengine Ultra AX machines, interrupt numbers are not mapped
   at all, and full interrupt numbers (not just INOs) are given in
   the interrupt properties. This is more or less cosmetical; the
   PCI interrupt numbers would be wrong, but the psycho resource
   allocation method would pass the right numbers on anyway.

Tested by:	mux (1), Maxim Mazurok <maxim@km.ua> (2)
2002-11-07 16:07:46 +00:00
Thomas Moestl
7c3563be7b Add "pci108e,8000" (psycho) and "pci108e,a000" (US-IIi sabre) to the list of
recognized compat properties. This should make the psycho driver attach
properly on SPARCengine Ultra AX machines.
Switch to a table-driven logic to recognize the ID's, since their number
is now large enough to justify this.

These changes are analogous to those made in NetBSD r.1.35, but
implemented a bit differently.
2002-10-16 17:37:50 +00:00
Thomas Moestl
69593fa999 Use a linked list to keep the psycho softcs instead of a statically
sized array.
While being there, deuglify the psycho pair detection loop which became
quite awkward in a previous code reorganization.
2002-10-16 17:03:36 +00:00
Jake Burkholder
3297e8c990 Renamed intr_enqueue to intr_vector and intr_dequeue to intr_fast, to
better reflect how they are called.
2002-09-28 03:06:35 +00:00
Thomas Moestl
f42d907165 When multiple IOMMUs are present in a system, use a single TSB for all
of them, and couple them by always performing all operations on all
present IOMMUs. This is required because with the current API there
is no way to determine on which bus a busdma operation is performed.

While being there, clean up the iommu code a bit.

This should be a step in the direction of allow some of larger machines
to work; tests have shown that there still seem to be problems left.
2002-07-16 18:17:03 +00:00
Thomas Moestl
5fb49f9fd6 Add PCI bus enumeration and latency timer setup to the sparc64 MD PCI
code. Both tasks are not always performed completely by the firmware.
The former is required to get some e450 models to boot; the latter fixes
the repeated fifo underruns with hme(4)s and gem(4)s observed on some
machines (and probably performance problems with other peripherals as
well).
2002-06-12 19:20:57 +00:00
Thomas Moestl
3191e556ea Do not try to set up the PCI bus B error interrupt on "sabre"s, since
it is only available on "psycho"s. The same applies to the power
management interrupt, which is not enabled by default though.
2002-04-02 17:27:35 +00:00
Thomas Moestl
e8e2c56650 Revamp the busdma implementation a bit:
- change the IOMMU support code so that it supports overcommittting the
  available DVMA memory, while still allocating as lazily as possible.
  This is achieved by limiting the preallocation, and deferring the
  allocation to map load time when it fails. In the latter case, the
  DVMA memory reserved for unloaded maps can be stolen to free up enough
  memory for loading a map.
- allow NULL settings in the method tables, and search the parent tags
  until an appropriate implementation is found. This allows to remove some
  kluges in the old implementation.
2002-03-24 02:50:53 +00:00
Thomas Moestl
464ae30ee6 Make the OpenFirmware interrupt mapping code more generic, to reduce
the bus-dependent code and to be able to support more systems. The core
of the new code is mostly obtained from NetBSD.
Kluge the interrupt routing methods of the psycho and apb drivers so
that an intline of 0 can be handled for now; real routing is still not
possible (all intline registers are preinitialized instead); this will
require a sparc64-specific adaption of the driver for generic PCI-PCI
bridges with a custom routing method to work right.
2002-03-24 02:11:06 +00:00
Thomas Moestl
1734bea4fb Map the device memory belonging to resources of type SYS_RES_MEMORY into
KVA upon activation so that rman_get_virtual() works as expected.
2002-03-24 01:51:29 +00:00
Thomas Moestl
4b5504494d Add code to print the fault virtual address for uncorrectable DMA errors
caused by IOMMU misses to aid debugging. This will only work on
UltraSPARC-IIi and IIe.
2002-03-23 20:42:23 +00:00
Thomas Moestl
bc4e9bed7c Add PCIfunctions 2 and 3 of the PCIO2 chip to the intpin quirk table. 2002-03-23 20:04:10 +00:00
Jake Burkholder
76cf1369d7 Add a DEBUGGER_ON_POWERFAIL option. This makes the power button on ultra 10s
work like an NMI button.
2002-03-13 05:58:45 +00:00
Thomas Moestl
e37d222c43 Merge r1.39 from NetBSD (manage both streaming caches for psycho pairs).
Use explicit bus space accesses instead of mapping the device memory
into kva.
Fix support for psycho pairs, and catch up with iommu code changes.
2002-02-13 16:07:59 +00:00
Thomas Moestl
95c7d7d47e Don't panic when no interrupt map can be found for a PCI bus; this seems
to happen on some models, like the Netra T1.
2002-02-13 15:44:58 +00:00
Thomas Moestl
ca8712b098 Correct the defintion of struct ofw_upa_regs, and use it instead of
struct ofw_nexus_reg. Implement UPA device memory management in the
nexus driver.
Adapt the psycho driver to these changes, and do some minor cleanup work
while being there.
2002-01-02 18:27:13 +00:00
Thomas Moestl
db8a25bd07 Do not include pcib.h, which only existed in my development tree, and do
not use struct pcib_softc when struct apb_softc would be correct.

Spotted by:	jake
Pointy hat to:	tmm
2001-12-30 16:14:33 +00:00
Thomas Moestl
70527a680b Add a workaround for quirky PCI devices that set the intpin register to
0, but use this mechanism to generate interrupts.
Preserve the child device when setting up and tearing down interrupts.
Some style nits.
2001-12-21 21:35:47 +00:00
Thomas Moestl
caaed7acb7 Make the apb driver independent of the standard PCI bridge driver. 2001-12-21 21:28:54 +00:00
Thomas Moestl
a1dc822112 Add a file forgotten in the previous commit (a kobj interface that
defines methods that need to be implemented by sparc64 host bridge drivers).
2001-11-09 20:43:44 +00:00
Thomas Moestl
9d69e46260 Add support for the Sun psycho/sabre UPA-PCI bridge, some OpenFirmware
PCI support code, and a driver for the Sun APB PCI-PCI bridge.
Partly ported from NetBSD.
2001-11-09 20:19:58 +00:00