- Make the USB hardware skip PTDs which are not allocated.
- Peek host memory twice. Sometimes the PTD status is incorrectly
returned as zero.
- Ensure the host channel is always freed when software TD
is completing.
- Add correct configuration of interrupt polarity and type.
- Set CERR to 2 for asynchronous traffic to avoid having to
reactivate the PTD when a NAK token is received.
- Fix detection of STALL PID.
Sponsored by: DARPA, AFRL
- Put "_LE_" into the register access macros to indicate little endian
byte order is expected by the hardware.
- Avoid using the bounce buffer when not strictly needed. Try to move
data directly using bus-space functions first.
- Ensure we preserve the reserved bits in the power down mode
register. Else the hardware goes into a non-recoverable state.
- Always use 32-bit access when writing or reading registers or FIFOs,
because the hardware is 32-bit oriented and don't really understand 8-
and 16-bit access.
- Correct writes to the memory address register. There is no need to
shift the register offset.
- Correct interval for interrupt endpoints.
- Optimise 90ns internal memory buffer read delay.
- Rename PDT into PTD, which is how the datasheet writes it.
- Add missing programming for activating host controller PTDs.
Sponsored by: DARPA, AFRL
- Need to set the pre-fetch memory address when reading the host memory.
- We currently assume that no endianness conversion is needed.
Sponsored by: DARPA, AFRL
