using the Rhine's internal shift registers which are designed
for the job. This reduces the amount of time we wait around shifting
bits, and seems to work better with some chips.
Also, provide a workaround for some newer cards which report fake PHYs
at multiple addresses. (As more cards are ID'd, I'm sure this part
of the code will have to be expanded to cover more cases.)
Submitted by: Thomas Nystrom <thn@saeab.se>
MFC after: 1 week
under load.
This patch has been tested by Thomas and other for more than a month now,
and all (known) hangs seem to be solved.
Thomas's explanation of the patch:
* Fix the problem with the printing of the RX-error.
* Code from if_fet do better deal with the RX-recovery including a
timeout of the RX-turnoff.
* The call to vr_rxeof before vr_rxeoc have been moved to a point
where the RX-part of the chip is turned off. Otherwise there is a
window where new data could have been written to the buffer chain
before the RX-part is turned off. If this happens the chip will see
a busy rx-buffer. I have no evidence that this have occured but
god knows what the chip will do in this case!
* I have added a timeout of the TX-turnoff. I have checked and in
my 900 MHz system the flags for turnoff (both RX & TX) is seen at
the first check in the loop.
* I could see that I got the VR_ISR_DROPPED interrupt sometimes and
started to thinking about this. I then realized that no recovery is
needed for this case and therefore I only count it as an rxerror
(which was not done before).
* Finally I have changed the FIFO RX threshhold to 128 bytes. When I
did this the VR_ISR_DROPPED interrupt went away. Theory: The chip
will receive a complete frame before it tries to write it out to
memory then the RX threshold is set to store'n'forward. IF the frame
is large AND the next rx frame also is large AND the bus is busy
transfering a TX frame to the TX fifo THEN the second received
frame wont fit in the FIFO and is then dropped. By having the RX
threshold set to 128 the RX fifo is emptied faster.
MFC after: 5 days
on 900B and 635(A).
Re-add the enhanced PHY access register method again for older chipsets,
they do not seem to work with all old chips.
Reviewed by: phk
MFC after: 7 days
- Add conversions to/from little endian for fields that the NIC accesses
by DMA as required.
- Add some bus_dmamap_sync() calls, and correct some existing ones.
- Read the receiver information from the EEPROM in an endian-neutral
manner.
- Load all RX and TX descriptors in a single DMA map up front, and
get the bus addresses of individual descriptors by address arithmetic;
this fixes multiple use of the descriptor tags, which would have
undesired effects.
It seems that xl still does not work on e250 boxen, for reasons which
are not clear yet.
Reviewed by: mux
and ether_ifattach() to end. This fixes a "could sleep" case and
simplifies error exit cases as well. Also be sure to set errno
and clean up resources in !mac error case.
Tested by: Ryan Beasley
Allow to read EEPROM from LAN. It is shared
between a 1394 controller and the NIC and each
time we access it, we need to set SIS_EECMD_REQ.
Idea from: linux driver source
Reviewed by: luoqi
Obtained from: linux driver source (idea)
register, and phy has to be directly accessed via mdio.
Patch converted to CURRENT from STABLE.
Submitted by: luoqi
Reviewed by: luoqi (again)
MFC after: 2 weeks
the PCI bus. When this bit is set, the Max DMA Burst Size
for TX/RX DMA should be no larger than 64 bytes.
Reviewed by: luoqi
Obtained from: (idea from linux driver source)
MFC after: 2 weeks
is read one clock edge too late. This bit is driven low by
slave (as any other input data bits from slave) when the clock
is LOW. The current code did read the bit after the clock was
driven high again.
Reviewed by: luoqi
MFC after: 2 weeks
bus_dmamap_load_mbuf() returned EFBIG.
o Fix mbuf leaks in an error (rare) code path.
o Reuse the TX descriptor if xl_encap() failed instead of
just picking the next one.
o Better error messages.
it possible to use this driver under ia64, sparc64 (though
there may be endianness issues with this one) and other archs.
Tested on: i386, alpha (gallatin)
pci_get_ether accesor, which gets it from the CIS for cardbus cards
(and from other pci-like buses via whatever mechanism is used there).
Submitted by: sam
Approved by: re (blanket)
1. Detect the revision of the Rhine chip we're using.
2. Use the force reset command on revisions which support
it whenever the normal reset command fails.
This should solve a wide range of "my vr0 locks up with reset
failed messages" problems. (Although the root causes should
be eventually tracked down.)
Tested by: grenville armitage <garmitage@swin.edu.au>
Obtained from: Via's if_fet driver
MFC after: 3 days
Approved by: re
o use if_input for input packet processing
o don't strip the Ethernet header for input packets
o use BPF_* macros bpf tapping
o call ether_ioctl to handle default ioctl case
o track vlan changes
Reviewed by: many
Approved by: re
