The core uart code expects the receive method to actually puts the
characters read into its buffers. For AT91, it's done in the ipend routine,
so also check if we have the alternate break sequence here.
MFC after: 3 days
Introduce framework to configure the multiplexed pins on boot.
Since the USART supprots RS-485 multidrop mode, it allows the
TX pins to float. However, for RS-232 operations, we don't
want these pins to float. Instead, they should be pulled up
to avoid mismatches. Linux does something similar when it
configures the TX lines. This implies that we also allow the
RX lines to float rather than be in the state they are left in
by the boot loader. Since they are input pins, I think that
this is the right thing to do.
Plus minor for our board.
address is in the userland address space. The proper thing is either to choose
a virtual address in the kernel address space beyond the KVA, or to use
pmap_mapdev().
Make serial ports more robust and reliable. Make non-console ports
work. This might have broken skyeye stuff.
o Introduce ping-pong receive buffers.
o Use DMA to copy characters directly into memory.
o Support baud rates other than 115200
o Use 1 stop bit when 1 stop bit is requested (otherwise 2 were used,
which caused dropped characters when received in bursts).
o Use 1.5 stop bits for 5-bit bytes, and 2 stop bits otherwise when 2
stop bits were requested.
o Actually update line parameters.
o Fix comments
o Move init into attach
o Tweaks to TX interrupt registers to get them reliable and non-storming.
o harvest data in ipend since the latency between it and the callback
was too long. This likely is how it should be, I don't know why I deferred
things to the callback before.
o disable all interrupts in console init. We don't want interrupts until
we turn on an ISR.
o cosmetic tweaks
o Automatically detect of the TIMEOUT interrupt is supported. If so, use
it so we get better CPU utilization. Otherwise do a character at a time
RX. Good news here is that it seems we have enough CPU and low enough
fast interrupt latency to do this reliably.
o Don't read USART_CR. It is a write-only register.
o start to implement bus_ioctl. Do BAUD now...
number of banks, rows and columns the SDRAMC is programmed to access
to determine the RAM size for the board, rather than hard-wiring it to
be 32MB. My company's board with 64MB now probes correctly, as does
the KB9202 with only 32MB. This means that to detect the right memory
size, our boot loader must correctly initialize these values. This is
a fairly safe assumption because the boot loader has to initialize
SDRAM already, and it isn't really possible to change this register
after we've accessed SDRAM.
The boot loader is supposed to leave this bit set to the right value
for the board. If this bit was set at attach time, use it to init the
config register correctly.
Note: this means the boot loader has to properly initialize it.
Add a new option, SKYEYE_WORKAROUNDS, which as the name suggests adds
workarounds for things skyeye doesn't simulate. Specifically :
- Use USART0 instead of DBGU as the console, make it not use DMA, and manually provoke an interrupt when we're done in the transmit function.
- Skyeye maintains an internal counter for clock, but apparently there's
no way to access it, so hack the timecounter code to return a value which
is increased at every clock interrupts. This is gross, but I didn't find a
better way to implement timecounters without hacking Skyeye to get the
counter value.
- Force the write-back of PTEs once we're done writing them, even if they
are supposed to be write-through. I don't know why I have to do that.
the wire. This increases the speed considerably. Start to put
infrastructure in place to do RX side, but that requires more study
before it can be done.
Add bus attachment for the ohci device on this chip. The bus and hub
are detected correctly, but the children devices aren't detected
correctly for reasons unknown.
o update TODO list
o Better use of busdma
o mark RX dtors as COHERENT. This helps performance a lot by not requiring
so many EXPENSIVE cache flushes. The cost of accessing it non-cached
is much smaller.
o Copy data from Rx buffers to make IP header 4 byte aligned.
o CRC length included in reported length, so cope
o Don't free TX buffer twice
o Manage TX buffers better.
o Enable just the interrupts we want.
o Manage OACTIVE better
# Some of these done by cognet
# These changes let us get to # via NFS root.
