Commit Graph

102 Commits

Author SHA1 Message Date
David E. O'Brien
61334e3b42 Use __FBSDID(). 2003-06-10 17:31:31 +00:00
Peter Wemm
c692fbe091 At great personal risk, add a __packed and __aligned(x) define that
expand to __attribute__((packed)) and __attribute__((aligned(x)))
respectively.  Replace the handful of gcc-ism's that use
__attribute__((aligned(16))) etc around the kernel with __aligned(16).

There are over 400 __attribute__((packed)) to deal with, that can come
later.  I just want to use __packed in new code rather than add more
gcc-ism's.
2002-09-23 05:55:10 +00:00
Andrew Gallatin
8bef1df9eb Remove ## concatination in the CFGREAD and CFGWRITE macros, as gcc3 complains
about them & they are not needed.  Same fix as to tsunami_pci.c.
(not surprising, as this code was cut and pasted from there when I wrote it).
2002-05-10 16:56:14 +00:00
Bernd Walter
27c5b6c8f1 Revive dec_axppci_33_intr_route for LCA.
We now get valid interrupt lines for devices on secondary pci busses.

Reviewed by:	gallatin
Approved by:	gallatin
2002-04-17 14:08:22 +00:00
Bernd Walter
dd516e0773 Clear the error flags in the LCA_IOC_STAT0 register after
machine_checks.
This fixes pci config reads for non existing devices on secondary
pci busses.

Thanks to Andrew Gallatin for pointing me to the register

Reviewed by:	gallatin
Approved by:	gallatin
2002-04-17 13:57:50 +00:00
David E. O'Brien
200e654a4a I am not sure why ## was used in this macro, as w/o the string concatenation
the tokens are legal ANSI-C.  Maybe to enable 'op' to be a macro itself?
Anyway, with the ## concatenation Gcc 3.1's integrated `cpp' treats "=op("
as a single token vs. the three tokens it is.
2002-04-17 04:31:43 +00:00
Bernd Walter
0dc76ffdd4 LCA based systems can't handle more than 16 devices on pci bus 0.
Reviewed by:	gallatin
Approved by:	gallatin
2002-04-11 13:24:20 +00:00
Andrew Gallatin
ddf23aa842 shut up the compiler 2002-03-21 18:48:00 +00:00
Warner Losh
b70c0e8b00 Fix abuses of cpu_critical_{enter,exit} by converting to
intr_{disable,restore} as well as providing an implemenation of
intr_{disable,restore}.
2002-03-21 06:14:58 +00:00
David E. O'Brien
d0ce7d0078 Remove __P(). This was tested on the GENERIC kernel. 2002-03-20 18:58:47 +00:00
Andrew Gallatin
030cb46918 recover from namespace collision caused by un-static'ing pci_alloc_resource()
in rev  1.187 of sys/dev/pci/pci.c
2002-02-28 18:18:41 +00:00
John Baldwin
98f9879242 Introduce a standard name for the lock protecting an interrupt controller
and it's associated state variables: icu_lock with the name "icu".  This
renames the imen_mtx for x86 SMP, but also uses the lock to protect
access to the 8259 PIC on x86 UP.  This also adds an appropriate lock to
the various Alpha chipsets which fixes problems with Alpha SMP machines
dropping interrupts with an SMP kernel.
2001-12-20 23:48:31 +00:00
John Baldwin
7e1f6dfe9d Modify the critical section API as follows:
- The MD functions critical_enter/exit are renamed to start with a cpu_
  prefix.
- MI wrapper functions critical_enter/exit maintain a per-thread nesting
  count and a per-thread critical section saved state set when entering
  a critical section while at nesting level 0 and restored when exiting
  to nesting level 0.  This moves the saved state out of spin mutexes so
  that interlocking spin mutexes works properly.
- Most low-level MD code that used critical_enter/exit now use
  cpu_critical_enter/exit.  MI code such as device drivers and spin
  mutexes use the MI wrappers.  Note that since the MI wrappers store
  the state in the current thread, they do not have any return values or
  arguments.
- mtx_intr_enable() is replaced with a constant CRITICAL_FORK which is
  assigned to curthread->td_savecrit during fork_exit().

Tested on:	i386, alpha
2001-12-18 00:27:18 +00:00
Andrew Gallatin
e47b20bee2 - splhigh()/splx() -> critical_enter()/critical_exit()
- fix KV macro in t2_pci.c to include the sable_lynx_base variable
so that the T2 CSRs can be found on lynxes.   Current should be
bootable on lynxes now.
2001-10-20 21:05:14 +00:00
John Baldwin
e37d2a8c82 Remove unneeded sys/mutex.h includes. 2001-10-19 19:23:32 +00:00
Matt Jacob
1aaf1de145 Fix Assembler buglet: Warning: .end directive names different symbol than .ent
MFC after:	2 weeks
2001-06-14 19:33:16 +00:00
Andrew Gallatin
abeba9a6bc Supply the intpin to the platform.pci_intr_map() function. It turns
out nearly every platform but the one I tested on requires the intpin
to swizzle out the correct intline.

tested by: Martijn Pronk <mpkisbkl@xs4all.nl> (lca_pci)
2001-06-10 19:18:51 +00:00
Andrew Gallatin
150cd07213 Resurrect platform.pci_intr_map() and essentially undo the effects of
the interface conversion to platform.pci_intr_route().  I've left the
platform.pci_intr_route() function pointer in place, as well as
alpha_pci_route_interrupt(), but no platform currently implements it.

To work around the removal of alpha_platform_assign_pciintr(cfg);
from the pci probe code, I've hooked in calls to platform.pci_intr_map()
in pcib_read_config (similar to the x86 APIC_IO ifdef in pci_cfgregread)
for every chipset that has a platform which needs it.

While here, I've removed the interupt mapping/routing code from the
AS2x00 platform because its not required (it has never been present in
-stable).

Tested on: UP1000, Miata(GL), XP1000, AS2100, AS500
2001-06-01 17:39:11 +00:00
Andrew Gallatin
6dc5259a6c Backout previous revision. While it fixed many platforms, it broke
all alphas with devices behind ppb's.  I'm working on a better solution now.

Note that all alphas that use per-platform interrupt mapping are broken
again (as they have been for several months)
2001-05-31 21:47:25 +00:00
Andrew Gallatin
d6a516cf80 finally fix intr routing on alphas such as the as500 after months of
breakage:

- call PCIB_ROUTE_INTERRUPT() regardless of how valid the intline looks.
  Some alphas leave garbage in the intline and leave the intr mapping
  to OS platform support routines that map slots/buses to intlines
- Down in the alpha pci code, first try platform.pci_intr_route() and
  if it doesn't exist or returns garbage, just read the intline out of
  config space.

tested on AS500 (garbage in intline) and UP1000 (PC-like, intline is valid)

Note that a nice little hack like the APIC_IO section of pci_cfgregread()
is not workable.  This is because the calling interface for
alpha_pci_route_interrupt() requires us to figure out the bus/slot/etc
from a device_t.  At pci_read_device() time, we don't have a device_t
for the bus/slot/func in question.
2001-05-27 22:22:03 +00:00
Doug Rabson
a0e512b219 Make sure that all resource allocation is handled in the pcib device, not
the chipset. This is already how the multi-hose systems handle resource
allocation and it fixes a bug where dense and bwx memory allocations were
not handled properly.

Reviewed by: gallatin
2001-05-23 19:44:17 +00:00
Andrew Gallatin
29e7f33db5 fix alpha-MD compile errors after the vm_mtx commit 2001-05-20 16:22:46 +00:00
John Baldwin
0006681fe6 Switch from save/disable/restore_intr() to critical_enter/exit(). 2001-03-28 03:06:10 +00:00
John Baldwin
522be16a94 Use the MI ithread helper functions in the alpha hardware interrupt code. 2001-02-09 17:53:23 +00:00
Peter Wemm
03927d3c33 Send "#if NISA > 0" to the bit-bucket and replace it with an option.
These were compile-time "is the isa code present?" tests and not
'how many isa busses' tests.
2001-01-29 09:38:39 +00:00
Mike Smith
bb0d0a8efc Next phase in the PCI subsystem cleanup.
- Move PCI core code to dev/pci.
 - Split bridge code out into separate modules.
 - Remove the descriptive strings from the bridge drivers.  If you
   want to know what a device is, use pciconf.  Add support for
   broadly identifying devices based on class/subclass, and for
   parsing a preloaded device identification database so that if
   you want to waste the memory, you can identify *anything* we know
   about.
 - Remove machine-dependant code from the core PCI code.  APIC interrupt
   mapping is performed by shadowing the intline register in machine-
   dependant code.
 - Bring interrupt routing support to the Alpha
   (although many platforms don't yet support routing or mapping
   interrupts entirely correctly).  This resulted in spamming
   <sys/bus.h> into more places than it really should have gone.
 - Put sys/dev on the kernel/modules include path.  This avoids
   having to change *all* the pci*.h includes.
2000-12-08 22:11:23 +00:00
Andrew Gallatin
313231657d Partially re-write T2 chipset support based on Tru64 platform support
files which Compaq open-sourced (with a BSD license).

This commit adds support for proper PCI interrupt mapping and much
better support for swizzling between "standard" isa IRQs and the stdio
irqs used by the t2.  This also adds enabling/disabling/eoi support
for AlphaServer 2100A machines.  The 2100A (or lynx) interrupt
hardware is is very different (and much nicer) than the 2100.
Previously, only AS2100 and AS2000 machines worked.

This commits also lays the groundwork for supporting ExtIO modules.
These modules are essentially a second hose.  This work is left
unfinished pending testing on real hardware.  Wilko tells me that
ExtIO modules are quite rare, and may not actually exist in the wild.

Obtained from: Tru64
Tested by: wilko
2000-12-07 01:06:19 +00:00
Matt Jacob
b741a1c581 Fix for vanilla PC164 systems to use a slightly different PALcode magic
tweak to enable/disable interrupt sources. Seems to work. It is unclear
how many of the PC164 models actually might needs this, and whether or
not there are other hidden issues.

Obtained from:Bernd Walter <ticso@cicely8.cicely.de>
2000-12-04 17:21:46 +00:00
Andrew Gallatin
689634a3ea Convert the pcib_{read,write}_config args from signed to unsigned,
like the args to the config space accessors these functions replaced.

This reduces the likelyhood of overflow when the args are used in
macros on the alpha.  This prevents memory management faults when
probing the pci bus on sables, multias and nonames.

Approved by: dfr
Tested by: Bernd Walter <ticso@cicely8.cicely.de>
2000-12-01 15:27:48 +00:00
Andrew Gallatin
c75fa7f70c fix isa DMA on pyxis based machines:
- move the call to cia_init_sgmap() to after we've determined if we're a pyxis
- convert needed splhigh() in cia_sgmap_invalidate_pyxis() to disable_intr()

Previously, any isa DMA on a pyxis based machine would cause a panic
in cia_sgmap_invalidate_pyxis() because the pyxis workaround was never
setup.

- while i'm at it, convert needed splhigh() in cia_swiz_set_hae_mem to
disable_intr()
2000-11-21 03:25:31 +00:00
Matt Jacob
259515a1ec Fix typo in END macro (END'ed enable twice)
PR:		22713
Submitted by:	Bernd Walter <ticso@cicely5.cicely.de>
2000-11-09 17:01:21 +00:00
John Baldwin
a07b7a4e35 Pass in the new-bus flags to alpha_setup_intr(). 2000-11-01 18:40:42 +00:00
John Baldwin
1931cf940a - Heavyweight interrupt threads on the alpha for device I/O interrupts.
- Make softinterrupts (SWI's) almost completely MI, and divorce them
  completely from the x86 hardware interrupt code.
  - The ihandlers array is now gone.  Instead, there is a MI shandlers array
    that just contains SWI handlers.
  - Most of the former machine/ipl.h files have moved to a new sys/ipl.h.
- Stub out all the spl*() functions on all architectures.

Submitted by:	dfr
2000-10-05 23:09:57 +00:00
Matt Jacob
86b9bd5cdc Well, this works for me and I can now boot my PC164 again.
Nobody said it broke their system.
2000-09-11 21:10:25 +00:00
Andrew Gallatin
72f21cf2c5 A quick fix to get around a problem (described below) with cia based
machines.  The patch uses an existing global variable in place of the
newbus accessor to get at use_bwx.

This is a quick fix to get miatas booting again; somebody
with more newbus skills than I can muster will have to correct it.

Matt Jacob's description of the problem from the -alpha list:

The IVAR accessor stuff for pcib is incompletely specified for CIA. There's
only one accessor defined, and that's to get the BUS instance number.
<..>
The device methods that try and get at the use_bwx get overriden because
there's only one ivar for CIA's pcib, and that's for hose #, and it's always
zero.
2000-09-02 01:05:37 +00:00
Andrew Gallatin
cae70b8d4c Introduce explicit break statements in the various chipsets'
foo_pcib_[read|write]_config() functions rather than relying on
a break or return being in the CFG macro.

This fixes a panic later in the boot process on a UP1000.  From
inspection, it looks like this fixes a similar problem in the tsunami code.

Approved by: dfr
2000-08-31 16:19:27 +00:00
Andrew Gallatin
2d47df31fb fix a typo introduced by Doug's busspace changes that causes UP1000s to
crash very early in the boot process with a ksp not valid halt to the SRM.

submitted by: dfr
2000-08-31 16:11:20 +00:00
Doug Rabson
21c3015a24 * Completely rewrite the alpha busspace to hide the implementation from
the drivers.
* Remove legacy inx/outx support from chipset and replace with macros
  which call busspace.
* Rework pci config accesses to route through the pcib device instead of
  calling a MD function directly.

With these changes it is possible to cleanly support machines which have
more than one independantly numbered PCI busses. As a bonus, the new
busspace implementation should be measurably faster than the old one.
2000-08-28 21:48:13 +00:00
Matt Jacob
f919331938 Do the same thing for TurboLaser that was done for Rawhide- make room
for secondary (bridged) PCI busses by making primary PCI instances
16 units apart.
2000-07-10 02:40:49 +00:00
Matt Jacob
bc08581099 Don't let the infrastructure assign the 'next' PCI bus for us.
Instead, for now (until we get a pci infrastructure cleanup),
assign the PCI bus number to be mcpcia bus instance << 4. This
is to allow secondary bridges some room to be recongnized on
4100 systems.
2000-07-10 00:32:02 +00:00
John Baldwin
9701cd40b4 Support for unsigned integer and long sysctl variables. Update the
SYSCTL_LONG macro to be consistent with other integer sysctl variables
and require an initial value instead of assuming 0.  Update several
sysctl variables to use the unsigned types.

PR:		15251
Submitted by:	Kelly Yancey <kbyanc@posi.net>
2000-07-05 07:46:41 +00:00
Andrew Gallatin
72e9d2e8a2 Add support for the Alpha Processor, Inc. UP1000 system.
Reviewed by: dfr
Thanks to:  Alpha Processor Inc. for supplying the hardware.
2000-06-19 21:15:45 +00:00
Matt Jacob
79a4bee867 Sometimes there isn't an ISA bus configured. 2000-06-12 17:07:57 +00:00
Andrew Gallatin
4e5adf5f4a Part of AS2100 support that I neglected to commit last night
pointed out by: dfr
2000-05-28 17:52:08 +00:00
Andrew Gallatin
6ab09a6376 Add AlphaServer 2000 (demi-sable), 2100 (sable), and 2100A (lynx) support.
Only PCI and on-board ISA peripherials are supported at this time.

This support has been only lightly tested due to a lack of response to my
call for testers on the freebsd-alpha mailing list.  It works quite well
on the one AS2100 on which it has been tested, but it may not work on
an AS2100A and should therefore be regarded as experimental.
2000-05-28 02:52:54 +00:00
John Baldwin
7b7f33c4c3 Handle PCI devices that actually use an ISA IRQ for the cia and tsunami
chipsets.  An example of this is the USB controller on these chipsets.
With this, I can now use USB devices on the test Alpha I am borrowing at
the moment.

Reviewed by:	dfr, obrien
2000-05-10 18:54:28 +00:00
Matt Jacob
a9b64eeadb add in stubbie mcpcia_pci that will parent PCI busses 2000-05-07 04:59:30 +00:00
Peter Wemm
365c5db0a7 Add $FreeBSD$ 2000-05-01 20:32:07 +00:00
Matt Jacob
6499b39e60 Alpha 8200: Add in a dummy child of dwlpx so that we can make the leap
from DWLPX to PCI space. Just a methods holder such that we have a parent
which is a "pcib" and we create a child which is a "pci". Add the appropriate
ivar code (which is for a hose #).
2000-03-18 08:00:13 +00:00
Matt Jacob
9ca20275e0 Alpha 8200: Do some compilation cleanup. Conditionalize some IDE stuff
based upon presence/absence of ISA (there is no ISA bus on an 8200- okay,
well, there *could* be one in a DWLPX tray, but we don't support it)).

Most importantly change the interrupt resource map to cover a whole 16
bits. The 8200 uses 16 bit interrupt vectors which we construct that
contain the I/O-board, hose, an pci slot in them, and then we write these
vectors into the appropriate DWLPX registers. At any rate, a flat array
of 64 'IRQs' isn't enough.
2000-03-18 07:57:58 +00:00