This code seems to do exactly the same as ttydisc_rint_simple() does
nowadays. Just remove it.
Obtained from: //depot/user/ed/newcons/sys/dev/syscons/syscons.c
- Implement MSI support (MSIX support was already there)
- Use a table to drive MSI/MSIX exceptions
- Pre-calculate the command address instead of wasting cycles doing the
calculation on every i/o.
number of MSIX interrupts that are needed, and don't strictly check for 4.
Enable enough interrupt mask bits so that the controller will generate
interrupts in PERFORMANT mode. This fixes the hang-on-boot issues that
people were seeing with newer controllers.
we at least don't panic.
We don't really support dual role mode (INITIATOR/TARGET) any more. We
should but it's broken and will take a fair amount of effort to fix
and correctly manage both initiator and target roles sharing the port
database. So, for now, disallow it.
For some vague reason, it may be possible that scp->cursor_pos exceeds
scp->ysize * scp->xsize. This means that teken_set_cursor() may get
called with an invalid position. Just ignore the old cursor position in
this case.
Reported by: Paul B. Mahol <onemda gmail com>
MFC after: 1 month
- Improve newer AMD processor support (Family 0Fh Revision F and later).
- Adjust offset if DiodeOffet is set and valid. Note it is experimental
but it seems to give us more realistic temperatures. Newer Linux driver
blindly adds 21C for Family 0Fh desktop processors, however.
- Always populate dev.cpu and dev.amdtemp sysctl trees regardless of probe
order for consistency. Previously, dev.cpu.N.temperature was not populated
if amdtemp was loaded later than ACPI CPU driver and temperatures were not
accessible from dev.amdtemp.N.sensor0 tree for Family 10h/11h processors.
- Read the CPUID from PCI register instead of CPUID instruction to prevent
possible revision mismatches on multi-socket system.
- Change macros and variables to make them closer to AMD documents.
- Fix style(9) nits and improve comments.
Different sub-kinds of PCI buses may have different rules and
thus it is up for the bus backends to do proper input checks.
For example, PCIe allows configuration register numbers < 0x1000,
while for PCI proper the limit is 0x100.
And, in fact, the buses already do the checks.
Reviewed by: jhb
MFC after: 1 week
X-ToDo: add check for negative value to bus backends
X-ToDo: use named constant for maximum PCIe register
"set vesa mode" and higher 16bits of the flag would be the desired mode.
One can now set, for instance, hint.sc.0.flags=0x01680180, which means
that the system should set VESA mode 0x168 upon boot.
Submitted by: paradox <ddkprog yahoo com>, swell k at gmail.com with
some minor changes.
| grep <modname>' can be used instead.
Put a message behind bootverbose as
ichwd0: <Intel ICH6M watchdog timer> on isa0
ichwd0: Intel ICH6M watchdog timer (ICH6 or equivalent)
does not make a lot of sense.
MFC after: 1 week
where we figure out the hostname length under the lock, malloc the buffer
with the lock dropped, then recheck the length under the lock and loop again
if the buffer is now too small.
Tested by: Norbert Koch nkoch demig de
MFC after: 3 days
- Add vesa kernel options for amd64.
- Connect libvgl library and splash kernel modules to amd64 build.
- Connect manual page dpms(4) to amd64 build.
- Remove old vesa/dpms files.
Submitted by: paradox <ddkprog yahoo com> [1], swell k at gmail.com
(with some minor tweaks)
them from the old place. This commit necessary so that the tree would not
enter a broken state.
sys/i386/isa/vesa.c -> dev/fb/vesa.c
sys/i386/include/pc/vesa.h -> dev/fb/vesa.h
sys/i386/isa/dpms.c -> dev/dpms/dpms.c
"COMMAND 0x........ TIMEOUT AFTER .. SECONDS" messages. Any commands
that get truly stuck will still trigger the warning and the hardware
health check, just a little bit later.
# My reading of the docs suggests this can only happen on 10Base5 and
# 10Base2 setups (and maybe only the former), which I can't test
# adequately since I have nothing but 10BaseT, etc here.
requirements. It is busdma task, to manage proper alignment by loading
data to bounce buffers.
PR: kern/127316
Reviewed by: current@
Tested by: Ryan Rogers
