Commit Graph

436 Commits

Author SHA1 Message Date
Pyun YongHyeon
52ee8ac027 Increase the number of TX DMA segments from 32 to 35. It turned
out 32 is not enough to support a full sized TSO packet.
While I'm here fix a long standing bug introduced in r169632 in
bce(4) where it didn't include L2 header length of TSO packet in
the maximum DMA segment size calculation.

In collaboration with:	rmacklem
MFC after:		2 weeks
2014-03-31 01:54:59 +00:00
Marius Strobl
ad4328bac8 - Simplify MSI allocation and release. For a single one, we don't need to
fiddle with the MSI count and pci_release_msi(9) is smart enough to just
  do nothing in case of INTx.
- Don't allocate MSI as RF_SHAREABLE.

MFC after:	1 week
2013-12-29 17:43:37 +00:00
Pyun YongHyeon
67129934a9 Add support for BCM57764, BCM57767, BCM57782, BCM57786 and BCM57787.
Submitted by:	jhb
PR:	184304
2013-12-02 05:21:54 +00:00
Gleb Smirnoff
76039bc84f The r48589 promised to remove implicit inclusion of if_var.h soon. Prepare
to this event, adding if_var.h to files that do need it. Also, include
all includes that now are included due to implicit pollution via if_var.h

Sponsored by:	Netflix
Sponsored by:	Nginx, Inc.
2013-10-26 17:58:36 +00:00
Pyun YongHyeon
69b1f509a4 Fix for IPv4 fragment packets treated as RMCP.
bit25 of rxMode MAC register of 5762 needs to be set for rx mgmt
filter to work correctly when processing match for UDP header
fields.  Otherwise false positive can occur which causes IPv4
fragment to be received by APE instead of host.

Reported by:	Geans Pin <geanspin@broadcom.com>
2013-08-09 01:15:32 +00:00
Pyun YongHyeon
b77d3a3b8e 5725 family of devices corrupts TSO packets when TSO DMA buffers
cross into regions which are within MSS bytes of a 4GB boundary.
If we encounter the condition, drop the packet.

Reviewed by:	Geans Pin geanspin@Broacom
2013-07-22 05:45:54 +00:00
Pyun YongHyeon
2927f01f66 Add support for upcoming BCM5725 (ASIC 5762) controller. This is a
new 1Gb server controller chip that will be going into production
soon.
BCM5725 combines MAC with triple-speed PHY, a Network Controller
Sideband Interface (NC-SI) and on-chip memory buffer in a single
device.  BCM5725 has an Application Processing Engine (APE) that is
capable of on-chip management and offloading features.  BCM5725
supports high-precision clock, time stamp registers for
receive/transmit packets and programmable trigger inputs and
watchdog timeouts. These new features are not yet supported by
bge(4).
Many thanks to Broadcom for continuing to support FreeBSD!

Submitted by:	Geans Pin geanspin@Broacom (initial version)
Reviewed by:	Geans Pin geanspin@Broacom
H/W donated by:	Broadcom
2013-07-20 07:58:03 +00:00
Pyun YongHyeon
f8bb33c331 Setup the PCIE Fast Training Sequence (FTS) value to prevent
transmit hangs for 57766 and non Ax versions of 57765.
While here, correct definition of BGE_CHIPREV_57765_AX.
2013-07-20 07:09:50 +00:00
Pyun YongHyeon
29b44b096f Implement workaround for BCM5719/BCM5720 TX hang.
The read DMA request logic operation is based on having sufficient
available space in the transmit data buffer (TXMBUF) before a read
DMA can be requested.  There are four read DMA channels that use
the TXMBUF, and the logic checks if the available free space in the
TXMBUF is large enough for all the data in the four Send Buffers
for which buffer descriptors have been fetched.  The Enable_Request
signal is asserted only if the free TXMBUF space is larger than the
sum of the four DMA length registers.  The power-up default value
of BGE_RDMA_LSO_CRPTEN_CTRL register bit 25 (bit 21 on BCM5720) is
zero, which selects the DMA length registers to connect to the
input of the adder block.  The DMA length registers are
asynchronously reset following BCM5719/BCM5720 power-up, and due to
the lack of synchronous deassertion of the length registers reset
signal these resisters may contain uninitialized values following
the reset deassertion.
In the case of the failure the uninitialized DMA length register
values added up to more than the TXMBUF size, which prevented the
assertion of the Enable_Request signal and any subsequent read DMA
to start.  This lockup condition is the root cause of failing to
generate any transmit traffic.

To workaround the issue, select alternate output of multiplexers
and transmit the first four Ethernet frames. This overwrites the
DMA length registers with valid values.

Reported by:	Geans Pin <geanspin@broadcom.com>
Reviewed by:	Geans Pin <geanspin@broadcom.com>
2013-07-17 04:53:53 +00:00
Pyun YongHyeon
b584d2b3f4 Fix triggering false watchdog timeout as done in bce(4) when
controller is in PAUSE state.
2013-06-30 05:56:13 +00:00
Pyun YongHyeon
91bd90d8c2 Don't blidly clear GPIOs configuration. Just use firmware configured
one.  This change also fixes non-working traffic LED on BCM57780.

Submitted by:	Masanobu SAITOH <msaitoh@NetBSD.org>
Tested by:	Alexander Milanov <a@amilanov.com>
2013-06-26 01:15:40 +00:00
Pyun YongHyeon
4951ca8620 Fix a typo introduced in r213280. IFM_OPTIONS macro should see
current media word.
2013-06-14 05:16:51 +00:00
Pyun YongHyeon
0a2cc82713 Correct setting TX random backoff register. This register is
implemented as a 10 bits linear feedback shift register so only
lower 10 bits are valid.
Because this register is used to initialize random backoff interval
register only when resolved duplex is half-duplex, it wouldn't have
caused issues in these days.

Submitted by:	Masanobu SAITOH <msaitoh@NetBSD.org>
2013-06-07 01:21:09 +00:00
Pyun YongHyeon
b9d2edd7c8 Do not report current link status if driver is not running.
Reporting link status in driver has a side-effect that makes mii(4)
check current link status.  mii(4) will call link status change
callback when it sees link state change.  Normally this wouldn't
have problems. However, ASF/IPMI firmware can actively access PHY
regardless of driver's running state such that reporting link
status for not-running interface can generate meaningless link
UP/DOWN messages.

This change also makes dhclient think driver got a valid link
regardless of link establishment so it will bypass dhclient's
initial link status check. I think that wouldn't be issue
though.

Tested by:	Daniel Braniss <danny@cs.huji.ac.il>
2013-06-07 01:01:39 +00:00
Pyun YongHyeon
bd9c196a87 Fix a typo.
Reported by:	David Imhoff via brad@OpenBSD
Tested by:	hrs
Reviewed by:	davidch
2013-04-02 00:57:54 +00:00
Pyun YongHyeon
3dd76c98e4 r241438 broke IPMI access on Sun Fire X2200 M2(BCM5715).
Fix the IPMI regression by sending BGE_FW_DRV_STATE_UNLOAD to
ASF/IPMI firmware in driver attach phase.  Sending heartheat to
ASF/IPMI is enabled only after upping interface so
setting driver state to BGE_FW_DRV_STATE_START in attach phase
broke IPMI access.
While I'm here, add NVRAM arbitration lock before performing
controller reset. ASF/IPMI firmware may be able to access the NVRAM
while controller reset is in progress.  Without the arbitration
lock before resetting the controller, ASF/IPMI may not initialize
properly.

Special thanks to Miroslav Lachman who provided full remote
debugging environments.
2013-03-13 01:40:01 +00:00
Marius Strobl
2ad1b39662 Mention NetLink controllers in the fallback description, too. 2013-01-26 00:41:54 +00:00
Marius Strobl
d7acafa1e3 - Improve some comments.
- Make bge_lookup_{rev,vendor}() static.
- Factor out chip identification rather than duplicating the code.
- Sanitize bge_probe() a bit (don't hardcode buffer sizes, allow
  bge_lookup_vendor() to return NULL so the excessive panic() three
  can be removed there, etc.) and return BUS_PROBE_DEFAULT rather than
  hardcoding 0.
- According to the Linux tg3 driver, BCM57791 and BCM57795 aren't
  capable of Gigabit Ethernet.
- Check the return value of taskqueue_start_threads().
2013-01-26 00:11:39 +00:00
Pyun YongHyeon
0aba72dd91 bge_attach() can fail before attaching mii(4). So make sure to check
bge_miibus before detaching mii(4).
2013-01-24 04:54:53 +00:00
Pyun YongHyeon
3fc5fbfb0b For 57765 class controllers, set low watermark max receive frames to 1. 2013-01-24 02:25:43 +00:00
Gleb Smirnoff
c6499eccad Mechanically substitute flags from historic mbuf allocator with
malloc(9) flags in sys/dev.
2012-12-04 09:32:43 +00:00
Pyun YongHyeon
fe26ad88e3 Add preliminary support for BCM57766 ASIC.
While I'm here add BCM57762 device id which is found on Apple
Thunderbolt ethernet.

Tested by:	Richard Kuhns < rjk <> wintek dot com >
2012-11-30 01:38:00 +00:00
Dimitry Andric
29658c96ce Remove duplicate const specifiers in many drivers (I hope I got all of
them, please let me know if not).  Most of these are of the form:

static const struct bzzt_type {
	[...list of members...]
} const bzzt_devs[] = {
	[...list of initializers...]
};

The second const is unnecessary, as arrays cannot be modified anyway,
and if the elements are const, the whole thing is const automatically
(e.g. it is placed in .rodata).

I have verified this does not change the binary output of a full kernel
build (except for build timestamps embedded in the object files).

Reviewed by:	yongari, marius
MFC after:	1 week
2012-11-05 19:16:27 +00:00
Pyun YongHyeon
84c168f49a TCP/UDP checksum offloading feature for IP fragmented datagram was
removed in r99417.  bge(4) controllers can do TCP checksum offload
for IP fragmented datagrams but unlike ti(4), it lacks UDP checksum
offloading for IP fragmented datagrams. The problem was bge(4)
blindly requested TCP/UDP checksum for IP fragmented datagrams such
that it resulted in corrupted UDP datagrams before r99417.
Remove remaining code for TCP checksum offloading for IP fragmented
datagrams which should have been removed in r99417.
2012-11-01 06:02:27 +00:00
Pyun YongHyeon
d73ea7c6d3 For fast ethernet controllers, Ethernet@WireSpeed is not defined so
explicitly set BGE_PHY_NO_WIRESPEED flag.
2012-10-24 05:54:17 +00:00
Pyun YongHyeon
70c2071b92 Ethernet@WireSpeed is defined for 1000baseT adapter to establish a
link at a lower speed so enabling it for fiber adapters is wrong.
Fix the issue by setting BGE_PHY_NO_WIRESPEED such that brgphy(4)
wouldn't enable the feature.
While I'm here move PHY specific feature/bug configuration to new
location(just before mii attach) for readability.
2012-10-24 05:22:41 +00:00
Pyun YongHyeon
daeeb75cec Do not hardcode phy address. Multi-port controllers use different phy
address.
2012-10-24 05:00:56 +00:00
Pyun YongHyeon
548c8f1ac2 Add APE firmware support and improve firmware handshake procedure.
This change will enable IPMI access on 5717/5718/5719/5720 and 5761
controllers. Because ASF is not available when APE firmware is
present, bge_allow_asf tunable is ignored when driver detects APE
firmware.  Also bge(4) no longer performs two resets(one blind
reset and the other reset with firmware in mind) in device attach.
Now bge(4) performs a reset with enough information in bge_reset().
The APE firmware also needs special handling to make suspend/resume
work but it was not implemented yet.

With this change, bge(4) should work on any 5717/5718/5719/5720
controllers. Special thanks to Mike Hibler at Emulab who setup
remote debugging on Dell R820. Without his help I couldn't be able
to address several issues happened on Dell Rx20 systems. And many
thanks to Broadcom for continuing to support FreeBSD!

Submitted by:	davidch (initial version)
H/W donated by:	Broadcom
Tested by:	many
Tested on:	Del R820/R720/R620/R420/R320 and HP Proliant DL 360 G8
2012-10-11 06:43:43 +00:00
Pyun YongHyeon
cc085b3609 Rework controller reset procedure. Previously driver saved
BGE_PCI_PCISTATE register before issuing global reset. After
issuing reset, it reads BGE_PCI_PCISTATE register again and
compares the saved register value and current value. It was used to
know whether the global reset operation was completed or not.
Unfortunately, this logic caused several issues on recent BCM5717/
5718/5719 and BCM5720 controllers. It seems APE firmware accesses
some registers while global reset is in progress such that reading
BGE_PCI_PCISTATE register after reset does not yield old pre-reset
state value. This resulted in consuming too much time in global
reset and sometimes it couldn't successfully complete reset.

The BGE_MISCCFG_RESET_CORE_CLOCKS of BGE_MISC_CFG register is
self-clearing bit so driver is able to know the reset completion.
But the core-lock reset will disable indirect/flat/standard access
modes such that driver cannot poll BGE_MISCCFG_RESET_CORE_CLOCKS
bit of BGE_MISC_CFG register. So just wait enough time for
core-clock reset to complete.
Data sheet says driver should wait 100us for PCI/PCI-X devices and
100ms for PCIe devices. I chose 1ms for PCI/PCI-X since this value
was used for many years in bge(4). For PCIe devices, use 100ms as
recommended by data sheet.

bge_chipinit() also cleared BGE_MAC_MODE register which shall clear
firmware configured mode information. I think this will result in
losing ASF/IPMI link in device attachment. Let bge_reset() honor
firmware configured BGE_MAC_MODE register and don't announce driver
is UP in bge_reset(). Firmware should have control over driver until
it's fully initialized by driver.

While I'm here, enable workaround for PCI-X BCM5704 A0 in
bge_reset(). This will prevent internal arbitration logic from
switching to the other DMA engine after a retry cycle.
2012-10-11 05:48:04 +00:00
Pyun YongHyeon
87b8c39061 Remove unnecessary delay. I don't see any comments in data sheet
that requires 10ms delay after device reset.  Because that code was
there from day 1, I guess it was added to give enough settlement
time after updating BGE_MAC_MODE register.
The recommended delay time for BGE_MAC_MODE after updating is 40us
and it was already done in r241219.
2012-10-10 05:43:04 +00:00
Pyun YongHyeon
df4db53856 Fix a long standing VCPU reset sequence bug on BCM5906.
The VCPU(Virtual CPU) of BCM5906 is used to provide a mechanism to
control the bootcode execution and to pick up configuration data
stored inside the EEPROM.
The bootcode of BCM5906 will check the BGE_VCPU_STATUS_DRV_RESET
bit to decide which booting procedure to choose.
Data sheet indicates the VCPU of BCM5906 should set
BGE_VCPU_STATUS_DRV_RESET bit *before* VCPU reset or global reset.
2012-10-10 04:38:29 +00:00
Pyun YongHyeon
ad49eccff0 Do not force PCIe 1.0a mode in device reset on BCM5717 and newer
controllers. BCM5785 does not require PCI 1.0a mode as well during
reset.
2012-10-10 02:35:10 +00:00
Pyun YongHyeon
f846d3a23e Honor PHY type fiber for BCM5717/BCM5718/BCM5719/BCM5720. 2012-10-10 02:21:36 +00:00
Pyun YongHyeon
2246e8c6e8 On PHY write error use hex number to show the value.
Add more comments.
2012-10-10 01:59:53 +00:00
Pyun YongHyeon
48630d79c5 If the maximum payload size is 256 bytes or more, set the DMA write
water mark to 256 bytes.  Otherwise controller will encounter DMA
write under run errors and would result in RX DMA hang. If the
maximum payload size is 128 bytes, the water mark is set to 128
bytes as usual.
While here, set maximum read request size to 2048 for BCM5719/BCM5720.
For other PCIe devices, use 4096. And reprogram the maximum read
request size whenever device reset is performed.
2012-10-10 01:24:02 +00:00
Pyun YongHyeon
e010b05517 Rework device detach. While here, move driver lock/callout
initialization to the beginning of device attach for readability.
2012-10-08 07:33:43 +00:00
Pyun YongHyeon
f7add34cfc Limit applying TX data corruption and FIFO workaround to BCM5719
A0. It's believed BCM5720 does not have the issue.
2012-10-08 07:13:45 +00:00
Pyun YongHyeon
a6e66cd28b Follow Broadcom datasheet:
Delay 100 microseconds after enabling transmit MAC.
 Delay 10 microseconds after enabling receive MAC.
2012-10-05 07:13:21 +00:00
Pyun YongHyeon
9b80ffe78f Add 40 microseconds delay after updating EMAC Mode register as
recommended by Broadcom data sheet.
2012-10-05 06:24:22 +00:00
Pyun YongHyeon
a0a03d1e82 APE firmware touches EMAC Mode and TX/RX MAC Mode registers to keep
the MAC connected to the outside world.  So keep the accesses
atomic.
2012-10-05 03:46:25 +00:00
Pyun YongHyeon
e4146b9510 Don't touch EMAC Mode and TX/RX MAC Mode register when driver is
not running.
2012-10-05 03:35:38 +00:00
Gavin Atkinson
389c8bd51e Align the PCI Express #defines with the style used for the PCI-X
#defines.  This also has the advantage that it makes the names more
compact, iand also allows us to correct the non-uniform naming of
the PCIM_LINK_* defines, making them all consistent amongst themselves.

This is a mostly mechanical rename:
  s/PCIR_EXPRESS_/PCIER_/g
  s/PCIM_EXP_/PCIEM_/g
  s/PCIM_LINK_/PCIEM_LINK_/g

When this is MFC'd, #defines will be added for the old names to assist
out-of-tree drivers.

Discussed with:	jhb
MFC after:	1 week
2012-09-18 22:04:59 +00:00
Pyun YongHyeon
55b5758c90 Fix typo.
Submitted by:	Alexander Milanov < a <> amilanov dot com >
2012-06-07 03:22:20 +00:00
Marius Strobl
47f4a4dc9a Take advantage of nitems().
MFC after:	3 days
2012-06-02 19:41:28 +00:00
Pyun YongHyeon
198b3ad636 Remove unnecessary device_printfs.
Pointed out by:	marius
2012-05-31 23:56:10 +00:00
Marius Strobl
749a52693c Try to finally get the point in time at which bge_add_sysctls() is called
right; it needs to be called before bge_can_use_msi() but in turn requires
bge_flags to be properly set.

Submitted by:	yongari
MFC after:	3 days
2012-05-30 20:04:07 +00:00
Pyun YongHyeon
00b6d640df Don't force max payload size to 128. Root complex and Endpoint will
negotiate with each other on the TLP payload size so blindly
forcing the size to 128 can cause a completion error which in turn
will stop device.

Reported by:	Geans Pin < geanspin <> broadcom dot com >
MFC after:	5 days
2012-05-23 03:35:08 +00:00
Pyun YongHyeon
37ee7cc719 Make if_ierrors updated whenever any of the following counters are
updated.
 o Number of times NIC ran out of RX buffer descriptors
 o Number of inbound packet errors
 o Number of inbound packets that were chosen to be discarded
Previously only the discarded packet counter was used to update
if_ierrors.  This change fixes wrong if_ierrors counter on
BCM570[0-4] controllers.  For BCM5705 and later controllers bge(4)
already correctly counted it.

Reported by:	Eugene Grosbein <egrosbein <> rdtc dot ru>
2012-03-12 03:47:30 +00:00
Pyun YongHyeon
ea9c3a30f3 Show PCI bus speed and width as well as running mode of PCI-X
device in device attach.  This would help to narrow down issue to a
specific controller and operating mode of the controller.
While I'm here rename BGE_MISCCFG_BOARD_ID with
BGE_MISCCFG_BOARD_ID_MASK.
2012-03-12 02:42:47 +00:00
Pyun YongHyeon
062af0b00e Add workaround for PCI-X BCM5704 controller that live behind
AMD-8131 PCI-X bridge.  The bridge seems to reorder write access to
mailbox registers such that it caused watchdog timeouts by
out-of-order TX completions.

Tested by:	Michael L. Squires <mikes <> siralan dot org >
Reviewed by:	jhb
2012-03-12 02:09:47 +00:00