Fix p-state setting on Power8 by removing the accidental double-indirection of
the pstate_ids table.
The pstate_ids table comes from the OF property "ibm,pstate-ids." On Power9,
the values happen to be identical to the indices, so the extra indirection was
harmless. On Power8, the values were out of the range [0, npstates], so
pmcr_set() would fail the spec[0] range check with EINVAL.
While here, include both the value and index in the driver-specific register
array as spec[0] and spec[1] respectively. They're redundant, but relatively
harmless, and it may aid debugging.
While here, fix the range check to exclude the index npstates, which is one
past the last valid index.
PR: 233693
Reported and tested by: sbruno
Reviewed by: jhibbits
Summary: POWER8 and POWER9 use a single CPU register, per core, to change clock
speed. Everything else is handled by the on-chip controller. This change
necessitates a change to the cpufreq global kernel driver to bump supported
levels, as the device tree for these systems can have theoretically 256
different options. On my POWER9 Talos, the list consists of 100 items. At
16.67MHz intervals, that allows for a change of roughly 1.67GHz between lowest
and highest.
This has only been tested on the POWER9. However, since they're similar, this
should work on POWER8 as well.
Reviewed By: nwhitehorn
Differential Revision: https://reviews.freebsd.org/D15932
