Commit Graph

58 Commits

Author SHA1 Message Date
Philip Paeps
b0321bb1e7 Add basic support for the Marvell Orion TS-7800.
Submitted by:	Kristof Provost <kristof -at- freebsd.org>
2011-04-15 13:37:43 +00:00
Marcel Moolenaar
e4623c22fe Fix mv_gpio_in() for pin numbers that occupy bits 8-31 in GPIO registers.
The compiler will truncate the 32-bit return value of mv_gpio_value_get()
to match the 8-bit return value of mv_gpio_in(). A conditional expression
is used to have mv_gpio_in() always return 0 or 1 instead.
2011-03-16 00:42:15 +00:00
Marcel Moolenaar
078b894c69 In arm_get_next_irq(), use the last IRQ argument in order to prevent
a hard hang due to an interrupt storm or stuck interrupt pin. We
return the next IRQ that is larger than the last one returned and
in doing so give all interrupts a fair chance of being handled.
Consequently, we're able to break into the kernel debugger in such
an event.
2011-02-08 01:49:30 +00:00
Marcel Moolenaar
292e1140d1 o Make sure to mask off timer1 interrupts. It's not necessarily
masked-off by the firmware.
o   In DELAY(). Make sure we have an inner-loop body that the compiler
    cannot eliminate. While timing does not have to be perfect, the
    loops must be there to have at least some notion of delay.

Obtained from: Juniper Networks
2011-02-08 01:43:45 +00:00
Marcel Moolenaar
0d838e9ed0 Remove use_high from the softc and simply check the number of GPIO
pins to determine whether there's a high register set or not. This
allows platform_gpio_init() to work without duplicating the work
done in the attach method.
2011-02-07 05:36:32 +00:00
Marcel Moolenaar
1b96faf8fa The FDT describes the host controller directly. There's no need to
get properties from the parent. The parent is in fact the FDT bus
itself and will therefore not have the properties we're looking
for.

Sponsored by: Juniper Networks
2011-02-03 18:07:05 +00:00
Marcel Moolenaar
b2b953afee Fix r217688. We need to call init_param1() before we use msgbufsize,
now that the size of the message buffer is a tunable.
2011-01-22 01:31:59 +00:00
Marcel Moolenaar
4cdbe2b967 Fix backtraces by defining ksym_start & ksym_end if DDB is
defined. The kernel linker doesn't deal with symbols of
type NOTYPE and typically gives the wrong symbol ($a) for
local symbols.

Obtained from:  Juniper Networks, Inc.
2011-01-22 00:32:12 +00:00
Sergey Kandaurov
4053b05b91 Make MSGBUF_SIZE kernel option a loader tunable kern.msgbufsize.
Submitted by:	perryh pluto.rain.com (previous version)
Reviewed by:	jhb
Approved by:	kib (mentor)
Tested by:	universe
2011-01-21 10:26:26 +00:00
John Baldwin
31e55059be - Add a proper return value to mv_gpio_intr().
- Remove an obsolete use of INTR_FAST.
2011-01-06 21:03:55 +00:00
Alexander Motin
bda55b6adb Set of legacy mode SATA enchancements:
- Implement proper combined mode decoding for Intel controllers to properly
identify SATA and PATA channels and associate ATA channels with SATA ports.
This fixes wrong reporting and in some cases hard resets to wrong SATA ports.
- Improve SATA registers support to handle hot-plug events and potentially
interface errors. For ICH5/6300ESB chipsets these registers accessible via
PCI config space. For later ones they may be accessible via PCI BAR(5).
- For controllers not generating interrupts on hot-plug events, implement
periodic status polling. Use it to detect hot-plug on Intel and VIA
controllers. Same probably could also be used for Serverworks and SIS.
2010-10-18 11:30:13 +00:00
Alexander Motin
afc1cdb92d Clear timer interrupt status before calling callback, not after it,
This fixes timer interrupt losses, fatal in one-shot mode.
2010-09-18 13:44:39 +00:00
Alexander Motin
599cf0f197 Fix several un-/signedness bugs of r210290 and r210293. Add one more check. 2010-07-20 15:48:29 +00:00
Alexander Motin
e9f0d5658c Refactor Marvell ARM SoC timer driver to the new timer infrastructure. 2010-07-20 11:46:45 +00:00
Rafal Jaworowski
294e2f046a Now that we are fully FDT-driven on MRVL platforms, remove PHYSMEM_SIZE option. 2010-07-19 19:19:33 +00:00
Rafal Jaworowski
4f124b977c Eliminate FDT_IMMR_VA define.
This removes platform dependencies from <machine>/fdt.h for the benfit of
portability.
2010-07-19 18:47:18 +00:00
Rafal Jaworowski
5710b7a9da Move MRVL FDT fixups and PIC decode routine to a platform specific area.
This allows for better encapsulation (and eliminates generic fdt_arm.c, at
least for now).
2010-07-19 18:41:50 +00:00
Rafal Jaworowski
db5ef4fc77 Convert Marvell ARM platforms to FDT convention.
The following systems are involved:

  - DB-88F5182
  - DB-88F5281
  - DB-88F6281
  - DB-78100
  - SheevaPlug

This overhaul covers the following major changes:

  - All integrated peripherals drivers for Marvell ARM SoC, which are
    currently in the FreeBSD source tree are reworked and adjusted so they
    derive config data out of the device tree blob (instead of hard coded /
    tabelarized values).

  - Since the common FDT infrastrucutre (fdtbus, simplebus) is used we say
    good by to obio / mbus drivers and numerous hard-coded config data.

Note that world needs to be built WITH_FDT for the affected platforms.

Reviewed by:	imp
Sponsored by:	The FreeBSD Foundation.
2010-06-13 13:28:53 +00:00
Alexander Motin
dd48af360f Import mvs(4) - Marvell 88SX50XX/88SX60XX/88SX70XX/SoC SATA controllers
driver for CAM ATA subsystem. This driver supports same hardware as
atamarvell, ataadaptec and atamvsata drivers from ata(4), but provides
many additional features, such as NCQ, PMP, etc.
2010-05-02 19:28:30 +00:00
Alexander Motin
0295bbe76f Oops! Wrong copy-paste in r206053. 2010-04-01 19:05:43 +00:00
Alexander Motin
4703a67a9a Fill extended ATA command registers in cPRD to support 48bit commands. 2010-04-01 18:17:53 +00:00
Rafal Jaworowski
bd50890544 Provide correct TCLK value for Kirkwood A1 silicon revision.
While there improve SOC ID output accordingly.

Obtained from:	Semihalf
MFC after:	1 week
2010-03-05 19:45:45 +00:00
Rafal Jaworowski
a9024075a7 Do not force verbose and single mode in non-metadata boot case.
We want to go multi-user by default also in case of booting without loader(8).
2010-02-24 20:31:00 +00:00
Alexander Motin
402ea18cbd Fix the build. 2009-12-08 21:42:04 +00:00
Alexander Motin
066f913a94 MFp4:
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this options deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.

As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.atapi_dma tunable work again.

Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.

Submitted by:	nwitehorn (powerpc part)
2009-12-06 00:10:13 +00:00
Alan Cox
c346328f95 Eliminate an unnecessary vm include file. 2009-11-04 04:41:03 +00:00
Alexander Motin
ebbb35ba70 MFp4:
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.
2009-10-31 13:24:14 +00:00
Marcel Moolenaar
191bb483f2 Review previous change. It has no relation to the I-cache coherency
changes and thus unintentional.

Spotted by: rdivacky@
2009-10-21 18:44:00 +00:00
Marcel Moolenaar
1a4fcaebe3 o Introduce vm_sync_icache() for making the I-cache coherent with
the memory or D-cache, depending on the semantics of the platform.
    vm_sync_icache() is basically a wrapper around pmap_sync_icache(),
    that translates the vm_map_t argumument to pmap_t.
o   Introduce pmap_sync_icache() to all PMAP implementation. For powerpc
    it replaces the pmap_page_executable() function, added to solve
    the I-cache problem in uiomove_fromphys().
o   In proc_rwmem() call vm_sync_icache() when writing to a page that
    has execute permissions. This assures that when breakpoints are
    written, the I-cache will be coherent and the process will actually
    hit the breakpoint.
o   This also fixes the Book-E PMAP implementation that was missing
    necessary locking while trying to deal with the I-cache coherency
    in pmap_enter() (read: mmu_booke_enter_locked).

The key property of this change is that the I-cache is made coherent
*after* writes have been done. Doing it in the PMAP layer when adding
or changing a mapping means that the I-cache is made coherent *before*
any writes happen. The difference is key when the I-cache prefetches.
2009-10-21 18:38:02 +00:00
Rafal Jaworowski
7ec5aa41ca Introduce SheevaPlug support.
- The device is based on Marvell 88F6281 system on chip.
  - More info about the platform at http://www.plugcomputer.org

  - To build the FreeBSD kernel:
    make buildkernel TARGET_ARCH=arm KERNCONF=SHEEVAPLUG

  - Installation notes at: http://wiki.freebsd.org/FreeBSDMarvell

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 10:09:25 +00:00
Rafal Jaworowski
c0d853f6b9 Exclude common Kirkwood settings so they can be shared among various platforms
based on this SOC. This is a preliminary step for SheevaPlug support.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:39:11 +00:00
Rafal Jaworowski
5694b144c0 Properly handle initial state of power mgmt.
Modules on Marvell SOC can be selectively PM-disabled, and we must not access
disabled devices' registers (attempt to initialize them) unconditionally, as
this leads to the system hang. This patch introduces graceful handling of the
PM state during devices init.

Submitted by:	Michal Hajduk
Obtained from:	Semihalf
2009-08-25 09:35:50 +00:00
Rafal Jaworowski
a7817ce466 Eliminate platform_pmap_init() to simplify Marvell bootstrap code. 2009-08-25 09:30:03 +00:00
Rafal Jaworowski
f981547c99 Map DPCPU pages into ARM kernel VA space.
DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.

Submitted by:	Michal Hajduk, Piotr Ziecik
Reviewed by:	cognet, stas
Approved by:	re (kib)
Obtained from:	Semihalf
2009-07-01 20:07:44 +00:00
Rafal Jaworowski
ebeaf70342 Enable all populated TWSI (I2C) controllers on Marvell SOCs.
Obtained from:	Semihalf
2009-06-25 10:03:51 +00:00
Rafal Jaworowski
9d02143909 Introduce ata(4) support for Marvell integrated SATA controllers (found on
88F5xxx, 88F6xxx and MV78xxx system on chip devices).

Reviewed by:	stas
Obtained from:	Semihalf
2009-06-24 15:41:18 +00:00
Jeff Roberson
50c202c592 Implement a facility for dynamic per-cpu variables.
- Modules and kernel code alike may use DPCPU_DEFINE(),
   DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
   PCPU_*.  Requires only one extra instruction more than PCPU_* and is
   virtually the same as __thread for builtin and much faster for shared
   objects.  DPCPU variables can be initialized when defined.
 - Modules are supported by relocating the module's per-cpu linker set
   over space reserved in the kernel.  Modules may fail to load if there
   is insufficient space available.
 - Track space available for modules with a one-off extent allocator.
   Free may block for memory to allocate space for an extent.

Reviewed by:    jhb, rwatson, kan, sam, grehan, marius, marcel, stas
2009-06-23 22:42:39 +00:00
Marcel Moolenaar
85fc5c3b93 Move the memory layout definitions and logic from mvreg.h to mvwin.h
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.
2009-06-12 20:00:38 +00:00
Andriy Gapon
08d43f8e62 strict kobj signatures: number of fixes for arm architecture
no functional changes should result

Reviewed by:	imp, current@
Approved by:	jhb (mentor)
2009-06-11 17:05:13 +00:00
Marcel Moolenaar
272489fe59 Pass the previously returned IRQ back to arm_get_next_irq() so that
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.

Obtained from:	Juniper Networks, Inc.
2009-06-09 18:18:41 +00:00
Rafal Jaworowski
bc26e2e38f Adjust Marvell Discovery (MV78xxx) support to recognize newest chip revisions,
handle Z0 revision (early silicon) explicitly due to its quirks.

Obtained from:	Marvell, Semihalf
2009-04-16 11:20:18 +00:00
Andrew Thompson
68e3d00d68 Fix path and config name for ehci_mbus.c 2009-02-24 23:30:52 +00:00
Marcel Moolenaar
78c0a9c9e2 Include Marvell EHCI HC driver for USB2. 2009-02-16 21:42:41 +00:00
Rafal Jaworowski
4e883c81d0 Check PCIE link status before accessing the bus.
Some 88F5182-based systems (Linkstation) have problems when PCIE is
accessed without any peripherals present.
2009-01-09 12:38:41 +00:00
Rafal Jaworowski
bc54686d20 Rename Marvell ARM CPU specific file according to r186933. 2009-01-09 10:55:33 +00:00
Rafal Jaworowski
e7be09420c Improve Marvell SOCs PCI/PCIE driver.
- Provide dedicated rmans for MEM and IO resources.

- Convert PCI IRQ routing info into a table (from callback approach), provide
  config data for alternative DB- boards.

- Fix a wrong boundary check error in pcib_mbus_init_bar()

Obtained from:	Semihalf
2009-01-09 10:20:51 +00:00
Rafal Jaworowski
673c4fe419 Improve and extend Marvell SOCs platform code.
- Allow for setting per platform MPP/GPIO configuration in the kernel, so
  that we can override all settings firmware might set.

- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.

- Improve handling of USB controllers so that all port are available on the
  given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
  USB decode windows set-up.

- Other minor fixes and cosmetics.

Obtained from:	Semihalf
2009-01-08 18:31:43 +00:00
Rafal Jaworowski
aba47c3f81 Minor style(9) corrections. 2009-01-08 13:25:22 +00:00
Rafal Jaworowski
4a0180a3b2 Adjust Marvell SOC support for A0 chip revision.
- Clean up TCLK handling so that it's dynamically recognized depending on
  registers settings or chip version/revision. Update registers definitions.

- Teach SOC ident routine about A0 (initial silicon version for general
  audience)

Obtained from:	Marvell, Semihalf
2009-01-08 13:20:28 +00:00
Rafal Jaworowski
b09d6bf325 Avoid confusion and adjust link address range of Marvell Orion kernel so it is
the same as for Kirkwood and Discovery.
2008-12-05 15:31:51 +00:00