Enroll these drivers in multipass probing. The motivation behind this
is that the JBus to EBus bridges share the interrupt controller of a
sibling JBus to PCIe bridge (at least as far as the OFW device tree
is concerned, in reality they are part of the same chip) so we have to
probe and attach the latter first. That happens to be also the case
due to the fact that the JBus to PCIe bridges appear first in the OFW
device tree but it doesn't hurt to ensure the right order.
r197391: Add support for TX throttling
r198250: Move mxge(4)'s NIC watchdog reset handler from
a callout to a taskqueue
r198303: Make mxge do a better job recovering from NIC h/w faults
r200845: Don't take the driver mutex in mxge_tick()
r201758: Remove extraneous semicolons
* Support the L1D_CACHE_LD event on Core2 processors.
* Correct a group of typos: for Core2 programmable events, check
user supplied umask values against the correct event descriptor
field.
r200696:
Add rudimentary WOL support. While I'm here remove enabling
busmastering/memory address in resume path. Bus driver will handle
that.
r200740:
Swap VGE_TXQTIMER and VGE_RXQTIMER register definition. Pending
timer for Tx queue is at 0x3E.
r200756:
Correct fragment bit definition in comments.
r200758:
VT6130 datasheet was wrong. If VT6130 receive a jumbo frame the
controller will split the jumbo frame into multiple RX buffers.
However it seems the hardware always dma the frame to 8 bytes
boundary for the split frames. Only the first part of the fragment
can have 4 byte alignment and subsequent buffers should be 8 bytes
aligned. Change RX buffer the alignment requirement to 8 bytes from
4 bytes.
r200759:
Disable jumbo frame support for PCIe VT6130/VT6132 controllers.
Quite contrary to VT6130 datasheet which says it supports up to 8K
jumbo frame, VT6130 does not seem to send jumbo frame that is
larger than 4K in length. Trying to send a frame that is larger
than 4K cause TX MAC hang.
Even though it's possible to allow 4K jumbo frame for VT6130, I
think it's meaningless to allow 4K jumbo frame. I'm not sure VT6132
also has the same limitation but I guess it uses the same MAC of
VT6130.
r200972:
Remove wrong assertion.
Implement interrupt moderation scheme supported by VT61xx
controllers. TX/RX interrupt mitigation is controlled by
VGE_TXSUPPTHR and VGE_RXSUPPTHR register. These registers suppress
generation of interrupts until the programmed frames counter equals
to the registers. VT61xx also supports interrupt hold off timer
register. If this interrupt hold off timer is active all interrupts
would be disabled until the timer reaches to 0. The timer value is
reloaded whenever VGE_ISR register written. The timer resolution is
about 20us.
Previously vge(4) used single shot timer to reduce Tx completion
interrupts. This required VGE_CRS1 register access in Tx
start/completion handler to rearm new timeout value and it did not
show satisfactory result(more than 50k interrupts under load). Rx
interrupts was not moderated at all such that vge(4) used to
generate too many interrupts which in turn made polling(4) better
approach under high network load.
This change activates all interrupt moderation mechanism and
initial values were tuned to generate interrupt less than 8k per
second. That number of interrupts wouldn't add additional packet
latencies compared to polling(4). These interrupt parameters could
be changed with sysctl.
dev.vge.%d.int_holdoff
dev.vge.%d.rx_coal_pkt
dev.vge.%d.tx_coal_pkt
Interface has be brought down and up again before change take
effect.
With interrupt moderation there is no more need to loop in
interrupt handler. This loop always added one more register access.
While I'm here remove dead code which tried to implement subset of
interrupt moderation.
r200616:
Add new flag VGE_FLAG_SUSPENDED to mark suspended state and
remove suspended member in softc.
r200617:
Add "Velocity" to probe message which will make it clearer which
ethernet controller was recognized. VIA consistently calls
"Velocity" family for gigabit ethernet controllers. For fast
ethernet controllers they uses "Rhine" family(vr(4) controllers))
and vr(4) already shows "Rhine" in probe message.
r200635:
Remove unused VGE_ETHER_ALIGN definition.
r200639:
Actually clear interrupts. Writing 0 has no effect.
r200644:
Remove unused member variable of softc.
r200551:
Whenever link state change interrupt is raised, vge_tick() is
called and vge(4) used to drive auto-negotiation timer(mii_tick) in
vge_tick(). Therefore the mii_tick was not called for every hz such
that auto-negotiation complete was never handled in vge(4).
Use mii_pollstat to extract current negotiated speed/duplex instead
of mii_tick. The latter is valid only for auto-negotiation case.
While I'm here change the confusing function name vge_tick() to
vge_link_statchg().
r200552:
Report media change result to caller instead of returning success
without regard to the result.
r200555:
Don't report current link status if interface is not UP.
If interface is not UP, the current link status wouldn't
reflect the negotiated status.
r200558:
Tell upper layer vge(4) supports long frames. This should be done
after ether_ifattach(), as ether_ifattach() initializes it with
ETHER_HDR_LEN.
While I'm here remove setting if_mtu, it's already handled in
ether_ifattach().
r200609:
All vge(4) controllers support RX/TX checksum offloading for VLAN
tagged frames so add checksum offloading capabilities. Also add
missing VLAN hardware tagging control in ioctl handler and let
upper stack know current VLAN capabilities.
r200613:
Rewrite RX filter setup and simplify code.
Now promiscuous mode and multicast handling is performed in single
function, vge_rxfilter().
r200538:
Introduce vge_flags member in softc. The vge_flags member will
record device specific bits. Remove vge_link and use vge_flags.
While here, move clearing link state before mii_mediachg() as
mii_mediachg() may affect link state.
r200540:
Save PHY address by reading VGE_MIICFG register. For PCIe
controllers(VT613x), we assume the PHY address is 1.
Use the saved PHY address in MII register access routines and
remove accessing VGE_MIICFG register.
While I'm here save PCI express capability register which will be
used in near future.
r200541:
Add MSI support for VT613x controllers.
r200543:
Increase output queue size from 64 to 255.
r200545:
We don't have to reload EEPROM in vge_reset(). Because vge_reset()
is called in vge_init_lock(), vge(4) always used to reload EEPROM.
Also add more comment why vge(4) clears VGE_CHIPCFG0_PACPI bit.
While I'm here add missing new line in vge_reset().
r200548:
Sort function prototyes.
r200526:
Use PCIR_BAR instead of hard-coded value.
r200527:
Fix typo in register definition.
r200529:
Clear VGE_TXDESC_Q bit for transmitted frames. The VGE_TXDESC_Q bit
seems to work like a tag that indicates 'not list end' of queued
frames. Without having a VGE_TXDESC_Q bit indicates 'list end'. So
the last frame of multiple queued frames has no VGE_TXDESC_Q bit.
The hardware has peculiar behavior for VGE_TXDESC_Q bit handling.
If the VGE_TXDESC_Q bit of descriptor was set the controller would
fetch next descriptor. However if next descriptor's OWN bit was
cleared but VGE_TXDESC_Q was set, it could confuse controller.
Clearing VGE_TXDESC_Q bit for transmitted frames ensure correct
behavior.
r200531:
Use ANSI function definations.
r200532:
Remove unnecessary return statement.
r200533:
s/u_intXX_t/uintXX_t/g
r200536:
style(9).
Overhaul bus_dma(9) usage and fix various things.
o Separate TX/RX buffer DMA tag from TX/RX descriptor ring DMA tag.
o Separate RX buffer DMA tag from common buffer DMA tag. RX DMA
tag has different restriction compared to TX DMA tag.
o Add 40bit DMA address support.
o Adjust TX/RX descriptor ring alignment to 64 bytes from 256
bytes as documented in datasheet.
o Added check to ensure TX/RX ring reside within a 4GB boundary.
Since TX/RX ring shares the same high address register they
should have the same high address.
o TX/RX side bus_dmamap_load_mbuf_sg(9) support.
o Add lock assertion to vge_setmulti().
o Add RX spare DMA map to recover from DMA map load failure.
o Add optimized RX buffer handler, vge_discard_rxbuf which is
activated when vge(4) sees bad frames.
o Don't blindly update VGE_RXDESC_RESIDUECNT register. Datasheet
says the register should be updated only when number of
available RX descriptors are multiple of 4.
o Use __NO_STRICT_ALIGNMENT instead of defining VGE_FIXUP_RX which
is only set for i386 architecture. Previously vge(4) also
performed expensive copy operation to align IP header on amd64.
This change should give RX performance boost on amd64
architecture.
o Don't reinitialize controller if driver is already running. This
should reduce number of link state flipping.
o Since vge(4) drops a driver lock before passing received frame
to upper layer, make sure vge(4) is still running after
re-acquiring driver lock.
o Add second argument count to vge_rxeof(). The argument will
limit number of packets could be processed in RX handler.
o Rearrange vge_rxeof() not to allocate RX buffer if received
frame was bad packet.
o Removed if_printf that prints DMA map failure. This type of
message shouldn't be used in fast path of driver.
o Reduce number of allowed TX buffer fragments to 6 from 7. A TX
descriptor allows 7 fragments of a frame. However the CMZ field
of descriptor has just 3bits and the controller wants to see
fragment + 1 in the field. So if we have 7 fragments the field
value would be 0 which seems to cause unexpected results under
certain conditions. This change should fix occasional TX hang
observed on vge(4).
o Simplify vge_stat_locked() and add number of available TX
descriptor check.
o vge(4) controllers lack padding short frames. Make sure to fill
zero for the padded bytes. This closes unintended information
disclosure.
o Don't set VGE_TDCTL_JUMBO flag. Datasheet is not clear whether
this bit should be set by driver or write-back status bit after
transmission. At least vendor's driver does not set this bit so
remove it. Without this bit vge(4) still can send jumbo frames.
o Don't start driver when vge(4) know there are not enough RX
buffers.
o Remove volatile keyword in RX descriptor structure. This should
be handled by bus_dma(9).
o Collapse two 16bits member of TX/RX descriptor into single 32bits
member.
o Reduce number of RX descriptors to 252 from 256. The
VGE_RXDESCNUM is 16bits register but only lower 8bits are valid.
So the maximum number of RX descriptors would be 255. However
the number of should be multiple of 4 as controller wants to
update 4 RX descriptors at a time. This limits the maximum
number of RX descriptor to be 252.
PR: kern/141276, kern/141414
Partial merge r198987:
Use device_printf() and if_printf() instead of printf() with an explicit
unit number and remove 'unit' members from softc.
Partial merge r199414:
Use the bus_*() routines rather than bus_space_*() for register operations.
r199543:
Several fixes to this driver:
- Overhaul the locking to avoid recursion and add missing locking in a few
places.
- Don't schedule a task to call vge_start() from contexts that are safe to
call vge_start() directly. Just invoke the routine directly instead
(this is what all of the other NIC drivers I am familiar with do). Note
that vge(4) does not use an interrupt filter handler which is the primary
reason some other drivers use tasks.
- Add a new private timer to drive the watchdog timer instead of using
if_watchdog and if_timer.
- Fixup detach by calling ether_ifdetach() before stopping the interface.
r200422:
Remove driver lock assertion in MII register access. This change
was made in r199543 to remove MTX_RECURSE. These routines can be
called in device attach phase(e.g. mii_phy_probe()) so checking
assertion here is not right as caller does not hold a driver lock.
Set the locally-assigned bit in the randomly generated Ethernet address
if we end up having to generate one.
PR: kern/133239
Discussed with: yongari
Approved by: ed (mentor, implicit)
r200088:
Add workaround to overcome hardware limitation which allows only a
single outstanding DMA read operation. Most controllers targeted to
client with PCIe bus interface(e.g. BCM5761) may have this
limitation. All controllers for servers does not have this
limitation.
Collapsing mbuf chains to reduce number of memory reads before
transmitting was most effective way to workaround this. I got about
940Mbps from 850Mbps with mbuf collapsing on BCM5761. However it
takes a lot of CPU cycles to collapse mbuf chains so add tunable to
control the number of allowed TX buffers before collapsing. The
default value is 0 which effectively disables the forced collapsing.
For most cases 2 would yield best performance(about 930Mbps)
without much sacrificing CPU cycles.
Note the collapsing is only activated when the controller is on
PCIe bus and the frame does not need TSO operation. TSO does not
seem to suffer from the hardware limitation because the payload
size is much bigger than normal IP datagram.
Thanks to davidch@ who told me the limitation of client controllers
and actually gave possible workarounds to mitigate the limitation.
r200227:
Remove PHY isolate/power down code in bge_stop(). The isolation
handler in brgphy(4) does not exist and brgphy(4) just resets the
PHY and returns EINVAL as it has no isolation handler. I also agree
on Marius's opinion that stop handler of every NIC driver seems to
be the wrong place for implementing PHY isolate/power down.
If we need PHY isolate/power down it should be implemented in
brgphy(4) and users should administratively down the PHY.
r200228:
Don't access jumbo frame related registers if controller lacks the
feature. These registers are reserved on controllers that have no
support for jumbo frame.
Only BCM5700 has mini ring so do not poke mini ring related
registers if controller is not BCM5700.
r200246:
Partially revert r200228. For mini RCB case, bge(4) still have to
disable mini ring withtout regard to mini ring support.
r200264:
Create sysctl node(dev.bge.%d.focred_collapse) instead of
hw.bge.forced_collapse. hw.bge.forced_collapse affects all bge(4)
controllers on system which may not desirable behavior of the
sysctl node. Also allow the sysctl node could be modified at any
time.
r201446:
Fix regression introduced in r198318. BCM5754/BCM5754M uses the
same ASIC ID of BCM5758 such that r198318 incorecctly enabled TSO
on BCM5754.BCM5754M controllers. BCM5754/BCM5754M needs a special
firmware to enable TSO and bge(4) does not support firmware based
TSO.
r199670:
Fix two long standing bugs on bge(4). Most pre BCM5755 controllers
have a DMA bug when buffer address crosses a multiple of the 4GB
boundary(e.g. 4GB, 8GB, 12GB etc). Limit DMA address to be within
4GB address for these controllers. The second DMA bug limits DMA
address to be within 40bit address space. This bug applies to
BCM5714 and BCM5715 and 5708(bce(4) controller). This is not
actually a MAC controller bug but an issue with the embedded PCIe
to PCI-X bridge in the device. So for BCM5714/BCM5715 controllers
also limit the DMA address to be within 40bit address space.
Special thanks to davidch@ who gave me detailed errata information.
I think this change will fix long standing bge(4) instability
issues on systems with more than 4GB memory.
r199671:
Implement TSO for BCM5755 or newer controllers. Some controllers
seem to require a special firmware to use TSO. But the firmware is
not available to FreeBSD and Linux claims that the TSO performed by
the firmware is slower than hardware based TSO. Moreover the
firmware based TSO has one known bug which can't handle TSO if
ethernet header + IP/TCP header is greater than 80 bytes. The
workaround for the TSO bug exist but it seems it's too expensive
than not using TSO at all. Some hardwares also have the TSO bug so
limit the TSO to the controllers that are not affected TSO issues
(e.g. 5755 or higher).
While I'm here set VLAN tag bit to all descriptors that belengs to
a frame instead of the first descriptor of a frame. The datasheet
is not clear how to handle VLAN tag bit but it worked either way in
my testing. This makes it simplify TSO configuration a little bit.
Big thanks to davidch@ who sent me detailed TSO information.
Without this I was not able to implement it.
r199674:
Add missing function prototype in r199671.
r199679:
Reduce status block size DMAed by controller. bge(4) uses single
Tx/Rx/Rx return ring such that large part of status block was not
used at all. All bge(4) controllers except BCM5700 AX/BX has a
feature to control the size of status block. So use minimum status
block size allowed in controller. This reduces number of DMAed
status block size to 32 bytes from 80 bytes.
r199761:
BGE_FLAG_40BIT_BUG should be set before creating DMA tags.
r199807:
Make sure one shot MSI is enabled.
r199808:
Fix typo which inversed the logic which in turn disabled MSI.
r199667:
Cache Rx producer/Tx consumer index as soon as we know status block
update and then clear status block. Previously it used to access
these index without synchronization which may cause problems when
bounce buffers are used. Also add missing bus_dmamap_sync(9) in
polling handler. Since we now update status block in driver, adjust
bus_dmamap_sync(9) for status block.
r199668:
For MSI case, interrupt is not shared and we don't need to force
PCI flush to get correct status block update. Add an optimized
interrupt handler that is activated for MSI case. Actual interrupt
handling is done by taskqueue such that the handler does not
require driver lock for Rx path. The MSI capable bge(4) controllers
automatically disables further interrupt once it enters interrupt
state so we don't need PIO access to disable interrupt in interrupt
handler.
r199663:
Due to newly added PCIe capabilities fallback code for finding the
PCIe capability did not work right on recent controllers. Remove
FreeBSD 6.x support code.
r199664:
Use capability pointer to access PCIe registers rather than
directly access them at fixed address. While I'm here don't touch
other bits of PCIe device control register except max payload size.
r199665:
Controller does not write Rx descriptors, remove BUS_DMASYNC_PREREAD.
r199666:
Rearrange bge_start_locked to see we can send more frames by
checking IFF_DRV_RUNNING and IFF_DRV_OACTIVE flags. Also if we
have less than 16 free send BDs set IFF_DRV_OACTIVE and try it
later. Previously bge(4) used to reserve 16 free send BDs after
loading dma maps but hardware just need one reserved send BD. If
prouder index has the same value of consumer index it means the Tx
queue is empty.
While I'm here check IFQ_DRV_IS_EMPTY first to save one lock
operation.
r199065:
Correct disabling checksum offloading for BCM5700 B0.
r199115:
Add missing bus_dmamap_sync(9) before issuing kick command.
r199116:
Zero out Tx/Rx descriptors before using them. Also add missing
bus_dmamap_sync(9) after Tx descriptor initialization.
r199153:
Controller does not update Tx descriptors(send BDs) after sending
frames so remove unnecessary BUS_DMASYNC_PREREAD and
BUS_DMASYNC_POSTREAD of bus_dmamap_sync(9).
r199661:
Remove extra white space.
r199662:
Fix typo introduced in r199011.
r198967:
Correct MSI mode register bits.
r199009:
bge(4) already switched to use UMA backed page allocator and local
memory allocator for jumbo frame was removed long time ago. Remove
no more used macros.
r199010:
Do bus_dmamap_sync call only if frame size is greater than
standard buffer size. If controller is not capable of handling
jumbo frame, interface MTU couldn't be larger than standard MTU
which in turn the received should be fit in standard buffer. This
fixes bus_dmamap_sync call for jumbo ring is called even if
interface is configured to use standard MTU.
Also if total frame size could be fit into standard buffer don't
use jumbo buffers.
r199011:
Reimplement Rx buffer allocation to handle dma map load failure.
Introduce two spare dma maps for standard buffer and jumbo buffer
respectively. If loading a dma map failed reuse previously loaded
dma map. This should fix unloaded dma map is used in case of dma
map load failure. Also don't blindly unload dma map and defer
dma map sync and unloading operation until we know dma map for new
buffer is successfully loaded. This change saves unnecessary dma
load/unload operation. Previously bge(4) tried to reuse mbuf
with unloaded dma map which is really bad thing in bus_dma(9)
perspective.
While I'm here update if_iqdrops if we can't allocate Rx buffers.
r199014:
Fix I mssied in r199011. Rx ring index also should be updated.
If we fill Rx ring full instead of half we can simplify this logic
but this requires more experimentation.
r199020:
Tell upper layer we support long frames. ether_ifattach()
initializes it to ETHER_HDR_LEN so we have to override it after
calling ether_ifattch().
While I'm here remove setting if_mtu value, it's initialized in
ether_ifattach().
r199035:
Don't count input errors twice, we always read input errors from
MAC in bge_tick. Previously it used to show more number of input
errors. I noticed actual input errors were less than 8% even for
64 bytes UDP frames generated by netperf.
Since we always access BGE_RXLP_LOCSTAT_IFIN_DROPS register in
bge_tick, remove useless code protected by #ifdef notyet.
r199036:
Count number of inbound packets which were chosen to be discarded
as input errors. Also count out of receive BDs as input errors.
r199054:
Partially revert r199035.
Revision 1.158 says only lower ten bits of
BGE_RXLP_LOCSTAT_IFIN_DROPS register is valid. For BCM5761 case it
seems the controller maintains 16bits value for the register.
However 16bits are still too small to count all dropped packets
happened in a second. To get a correct counter we have to read the
register in bge_rxeof() which would be too expensive.
r198923:
Use correct dma tag for jumbo buffer.
r198924:
Covert bge_newbuf_std to use bus_dmamap_load_mbuf_sg(9). Note,
bge_newbuf_std still has a bug for handling dma map load failure
under high network load. Just reusing mbuf is not enough as driver
already unloaded the dma map of the mbuf. Graceful recovery needs
more work.
Ideally we can just update dma address part of a Rx descriptor
because the controller never overwrite the Rx descriptor. This
requires some Rx initialization code changes and it would be done
later after fixing other incorrect bus_dma(9) usages.
r198927:
Remove common DMA tag used for TX/RX mbufs and create Tx DMA tag
and Rx DMA tag separately. Previously it used a common mbuf DMA tag
for both Tx and Rx path but Rx buffer(standard ring case) should
have a single DMA segment and maximum buffer size of the segment
should be less than or equal to MCLBYTES. This change also make it
possible to add TSO with minor changes.
r198928:
Make bge_newbuf_std()/bge_newbuf_jumbo() returns actual error code
for buffer allocation. If driver know we are out of Rx buffers let
controller stop. This should fix panic when interface is run even
if it had no configured Rx buffers.
Support the tablet in (at least) the Toshiba Portege M200 Tablet PC.
This device only appears on the ACPI bus, so isn't caught by the current
entry for it in the uart(4) ISA attachment.
PR: kern/140172
Reviewed by: jhb, marcel
Approved by: ed (mentor, implicit)
- Try pre-allocating all FIBs upfront. Previously we tried pre-allocating
128 FIBs first and allocated more later if necessary. Remove now unused
definitions from the header file[1].
- Force sequential bus scanning. It seems parallel scanning is in fact
slower and causes more harm than good[1]. Adjust a comment to reflect that.
- Rename the __tcpi_(snd|rcv)_mss fields of the tcp_info structure to remove
the leading underscores since they are now implemented.
- Implement the tcpi_rto and tcpi_last_data_recv fields in the tcp_info
structure.
Use the EVENTHANDLER system to hook into the usb device configuration and
perform a function such as ejecting a 3G autoinstaller disk. The eventhandler
system properly tracks threads and is safe to unload, remove the
setting/clearing of a function pointer in the kernel by u3g(4) which included a
tsleep for safety.
Add a quirk for the Curitel UM175 where setting multiplexing for call
management over the data endpoint causes communication to die.
Take this one step further and model it on the existing NetBSD quirk and import
other device IDs from them.
Obtained from: NetBSD
Fix hardware issue with FTDI chips: avoid sending a zero length packet due to
hardware sending garbage on ZLPs.
Reported by: Corey Smith
Submitted by: HPS
r199563:
Fix copy & paste error and remove extra space before colon.
r199608:
Remove unnecessary structure packing.
r199609:
Add initial endianness support. It seems the controller supports
both big-endian and little-endian format in descriptors for Rx path
but I couldn't find equivalent feature in Tx path. So just stick to
little-endian for now.
r199610:
Because we know received bytes including CRC there is no reason to
call m_adj(9). The controller also seems to have a capability to
strip CRC bytes but I failed to activate this feature except for
loopback traffic.
r199611:
Add IPv4/TCP/UDP Tx checksum offloading support. It seems the
controller also has support for IP/TCP checksum offloading for Rx
path. But I failed to find to way to enable Rx MAC to compute the
checksum of received frames.
r199612:
Add __FBSDID.
r199613:
Only Tx checksum offloading is supported now. Remove experimental
code sneaked in r199611.
r199558:
Use bus_{read,write}_4 rather than bus_space_{read,write}_4.
r199561:
Use capability pointer to access PCIe registers rather than
directly access them at fixed address. Frequently the register
offset could be changed if additional PCI capabilities are added to
controller.
One odd thing is ET_PCIR_L0S_L1_LATENCY register. I think it's PCIe
link capabilities register but the location of the register does
not match with PCIe capability pointer + offset. I'm not sure it's
shadow register of PCIe link capabilities register.
Remove complex macros that were used to compute bits values.
Although these macros may have its own strength, its complex
definition make hard to read the code.
Approved by: delphij
o Properly support M5229 revision 0xc7 and 0xc8:
- These revisions no longer have cable detection capability.
- The UDMA support bit of register 0x4b has been dropped without an
replacement.
- According to Linux it's crucial for working ATAPI DMA support to
also set the reserved bit 1 of regsiter 0x53 with these revisions.
o Only set ATA_CHECKS_CABLE for chip versions that actually support
cable detection, i.e. neither for ALI_OLD nor for ALI_NEW revisions
>= 0xc7.
Specify the capability and media bits of the capabilities page in
native, i.e. big-endian, format and convert as appropriate like we
also do with the multibyte fields of the other pages. This fixes
the output of acd_describe() to match reality on big-endian machines
without breaking it on little-endian ones. While at it, also convert
the remaining multibyte fields of the pages read although they are
currently unused for consistency and in order to prevent possible
similar bugs in the future.
Note that r200091 completely overrides r200053 and the merge of the
former is recorded for bookkeeping only.
r200091 won't be merged to 'more stable' branche(s) because of the POLA.
ndis_scan_results() can sleep if the scan results are not ready when
ndis_scan() is called. However, ndis_scan() is invoked from softclock()
and cannot sleep. Move ndis_scan_results() to the ndis driver's scan_end
hook instead.
Unbreak the ata_atapi() usage. Since r200171 (MFC'ed in r200432) the
mode setting functions get a ata_device type device passed instead of
a ata_channel one, thus ata_atapi() has to be adjusted accordingly.
Reviewed by: mav
Large I/Os on Promise controllers reported to cause UDMA ICRC errors and
subsequent timeouts. Restore previous limit for now, at least until
I will have hardware to experiment.
PR: kern/141438
- On entrance to the rx_eof sync RX rings maps with POSTWRITE flag
instead of POSTREAD: the hardware do not touch this memory (CPU
updates it). It is already synchronized as PREWRITE after the
processing is done.
- Add support for new BGE chips (5761, 5784 and 57780). These chips uses new
BGE_PCI_PRODID_ASICREV register to store the chip identifier and its revision.
- Add new grouping macro for 7575+ chips (BGE_IS_5755_PLUS).
- Add IDs for Fujitsu-branded Broadcom adapters.
Some general cleanup of scatter/gather memory allocation
- We don't need to check malloc return values with M_WAITOK
- remove variables that we don't really need
- cleanup the error paths by just calling drm_sg_cleanup()
- fix drm_sg_cleanup() to be safe to call at any time
Introduce ATA_CAM kernel option, turning ata(4) controller drivers into
cam(4) interface modules. When enabled, this option deprecates all ata(4)
peripheral drivers (ad, acd, ...) and interfaces and allows cam(4) drivers
(ada, cd, ...) and interfaces to be natively used instead.
As side effect of this, ata(4) mode setting code was completely rewritten
to make controller API more strict and permit above change. While doing
this, SATA revision was separated from PATA mode. It allows DMA-incapable
SATA devices to operate and makes hw.ata.(ata|atapi)_dma tunable work again.
Also allow ata(4) controller drivers (except some specific or broken ones)
to handle larger data transfers. Previous constraint of 64K was artificial
and is not really required by PCI ATA BM specification or hardware.
Submitted by: nwitehorn (powerpc part)
Limit maximum I/O size, depending on command set supported by device.
It is required to suppot non-LBA48 devices with MAXPHYS above 128K.
Same is done in ada(4).
Add counters for the i7 architecture which were accidentally left
out of the original commit of i7 support. These are all the counters
on pages A-32 and A-33 of the _Intel(R) 64 and IA32 Architectures
Software Developer's Manual Vol 3B_, June 2009. Almost all
of these counters relate to operations on the L2 cache.
Improve support for High-speed USB audio devices.
- fix issues regarding the mixer, where the interface number was not set in
time.
- fix wrong use of resolution parameter.
Submitted by: Hans Petter Selasky
Remove overuse of exclamation marks in kernel printfs, there mere fact a
message has been printed is enough to get someones attention. Also remove the
line number for DPRINTF/DPRINTFN, it already prints the funtion name and a
unique message.
Disable interrupts after doing early takeover of the usb controller in case usb
isnt actually compiled in (or kldloaded) as the controller could cause spurious
interrupts.
Improve High Speed slot allocation mechanism by moving the computation to the
endpoint rather than per xfer and provide functions around get/free of resources.
Submitted by: Hans Petter Selasky
ehci_init() will do reset and set the usbrev flag. Fix problem where
ehci_reset() was called before ehci_init().
PR: usb/140242
Submitted by: Sebastian Huber
- Add usb_fill_bulk_urb() and usb_bulk_msg() linux compat functions [1]
- Don't write actual length if the actual length pointer is NULL [2]
- correct Linux Compatibility error codes for short isochronous IN transfers
and make status field signed.
Submitted by: Leunam Elebek [1], Manuel Gebele [2]
updates device entries supported with the product name not magic numbers
and sorts entries. WUSB54GCV2 is added.
overhauls urtw(4) for supporting RTL8187B devices properly that there
was major changes to initialize RF chipset and set H/W registers and
removed a lot of magic numbers on code.
Reduce probe priority of USB input devices to BUS_PROBE_GENERIC from
BUS_PROBE_SPECIFIC. This allows device-specific drivers like atp to
attach reliably.
Do not ignore device interrupt if bus mastering is still active. It is
normal in case of media read error and some ATAPI cases, when transfer size
is unknown beforehand. PCI ATA BM specification tells that in case of such
underrun driver should just manually stop DMA engine. DMA engine should
same time guarantie that all bus mastering transfers completed at the moment
of driver reads interrupt flag asserted.
This change fixes interrupt storms and command timeouts in many cases.
PR: kern/103602, sparc64/121539, kern/133122, kern/139654
On Soft Reset, read device signature from FIS receive area, instead of
PxSIG register. It works better for NVidia chipsets. ahci(4) does the same.
PR: kern/140472, i386/138668
Explicitly acknowledge MSI completion, as required by SiI3124 datasheet.
It makes MSI working there. Later (and cheaper) PCIe chips (3132/3531)
still randomly crashing system in few seconds of high MSI rates, generating
something inaporopriate, like NMI or "Fatal trap 30".
Add Asynchronous Notification support for controllers without SNTF
capability by snooping SDB FIS receive area. It should be even faster
then regular way, but less reliable.
r199237:
sc->rev and is_offload(sc) will always be 0 during probe. Wait till
attach to get correct values.
r199238:
Make sure *some* edc is setup even for an unknown transceiver (assume
it is optical).
r199239:
The 10GBASE-T card should use an IPG of 1. Also enable the check
for low power startup on this card.
r199240:
Don't disable the XGMAC's tx on ifconfig down. It is unnecessary
and can cause false backpressure in the chip. Fix a us/ms mixup
while here.
r200003:
T3 firmware 7.8.0 for cxgb(4)
lindev(4) [1] is supposed to be a collection of linux-specific pseudo
devices that we also support, just not by default (thus only LINT or
module builds by default).
While currently there is only "/dev/full" [2], we are planning to see more
in the future. We may decide to change the module/dependency logic in the
future should the list grow too long.
This is not part of linux.ko as also non-linux binaries like kFreeBSD
userland or ports can make use of this as well.
Suggested by: rwatson [1] (name)
Submitted by: ed [2]
Discussed with: markm, ed, rwatson, kib (weeks ago)
Reviewed by: rwatson, brueffer (prev. version)
PR: kern/68961
Drop USB mass storage devices support from ata(4). It is out of the build as
long as I remember, and completely superseded by better maintained umass(4).
It's main idea was to optionally avoid CAM dependency for such devices, but
with move ATA to CAM, it is not actual any more.
No objections: hselasky@, thompsa@, arch@
- Extend XPT-SIM transfer settings control API. Now it allows to report to
SATA SIM number of tags supported by each device, implement ATA mode and
SATA revision negotiation for both SATA and PATA SIMs.
- Make ahci(4) and siis(4) to use submitted maximum tag number, when
scheduling requests. It allows to support NCQ on devices with lower tags
count then controller supports.
- Make PMP driver to report attached devices connection speeds.
- Implement ATA mode negotiation between user settings, device and
controller capabilities.
- Improve ATA mode/SATA revision control.
- fix a LOR between process lock and pmc thread mutex
- fix a system deadlock on process exit when the sample buffer
is full (pmclog_loop blocked in fo_write) and pmcstat exit.
It seems generation of link state change of e1000phy(4) is not
reliable on some Marvell PHYs. If msk(4) know it still does not
have established link check whether msk(4) missed the link state
change by looking into polled link state.
Reported by: Mel Flynn < mel.flynn+fbsd.current <> mailing.thruhere dot net >,
Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
Tested by: Gleb Kurtsou <gleb.kurtsou <> gmail dot com >
r198996:
Remove unnecessary header file.
r198997:
It's normal to see Rx FIFO overruns under high network load and
showing the message creates other side-effects. Remove the Rx
FIFO overrun message in interrupt handler. msk(4) should recover
from the FIFO overruns without any user intervention. Users can
still check the Rx FIFO overrun counter from MAC MIB statistics
maintained in driver(dev.msk.0.stats.rx.overflows).
Add a check to know whether driver is still running after
reacquiring driver lock in Rx handler. re(4) drops a driver lock
before passing received frame to upper stack and reacquire the
lock. During the time window ioctl calls could be executed and if
the ioctl was interface down request, driver will stop the
controller and free allocated mbufs. After that when driver comes
back to Rx handler again it does not know what was happend so it
could access free mbufs which in turn cause panic.
Reported by: Norbert Papke < npapk <> acm dot org >
Tested by: Norbert Papke < npapk <> acm dot org >
For AR8132 fast ethernet controller, do not report 1000baseT
capability to mii(4). Even though AR8132 uses the same model/
revision number of F1 gigabit PHY, the PHY has no ability to
establish 1000baseT link. I have no idea why Atheros use the same
device/model id for this PHY.
With this change atphy(4) does not report 1000baseT media
capability and manual 1000baseT configuration is also disabled
which is more desirable behavior for 10/100Mbps PHY.
Add DGE-560SX(Yukon XL) to the supported device list. Many thanks
to "Eugene Perevyazko <john <> dnepro dot net>" who kindly gave
remote access to system with DGE-560SX.
Add hack to pass controller specific information to phy driver.
Unlike most other PHYs there is no easy way to know which media
type the PHY supports on Marvell PHYs. MIIF_HAVEFIBER flags is now
passed via bus-specific instance variable of a device. While I'm
here add 88E1112 specific work around to set SIGDET polarity low.
Many thanks "Eugene Perevyazko <john <> dnepro dot net>" who kindly
gave remote access to system with DGE-560SX.
Add sysctls in ahd(4) in order to keep track of different classes of
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.
Sponsored by: Sandvine Incorporated
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.
Use only lower byte of sectors_intr IDENTIFY word as sector count.
This fixes SET_MULTI error during boot on devices supporting less then
16 sectors per interrupt.
