3 Commits

Author	SHA1	Message	Date
Neel Natu	c3498942a5	Restructure the MSR handling so it is entirely handled by processor-specific ... code. There are only a handful of MSRs common between the two so there isn't too much duplicate functionality. The VT-x code has the following types of MSRs: - MSRs that are unconditionally saved/restored on every guest/host context switch (e.g., MSR_GSBASE). - MSRs that are restored to guest values on entry to vmx_run() and saved before returning. This is an optimization for MSRs that are not used in host kernel context (e.g., MSR_KGSBASE). - MSRs that are emulated and every access by the guest causes a trap into the hypervisor (e.g., MSR_IA32_MISC_ENABLE). Reviewed by: grehan	2014-09-20 02:35:21 +00:00
Neel Natu	851d84f1b5	Add an option to ignore accesses by the guest to unimplemented MSRs. ... Also, ignore a couple of SandyBridge uncore PMC MSRs that Centos 6.4 writes to during boot. Reviewed by: grehan	2013-12-19 22:27:28 +00:00
Peter Grehan	366f60834f	Import of bhyve hypervisor and utilities, part 1. ... vmm.ko - kernel module for VT-x, VT-d and hypervisor control bhyve - user-space sequencer and i/o emulation vmmctl - dump of hypervisor register state libvmm - front-end to vmm.ko chardev interface bhyve was designed and implemented by Neel Natu. Thanks to the following folk from NetApp who helped to make this available: Joe CaraDonna Peter Snyder Jeff Heller Sandeep Mann Steve Miller Brian Pawlowski	2011-05-13 04:54:01 +00:00