Remove C99 initializers: they don't help in this case.
Set errno to 0 before strtoll() (from NetBSD).
PR: 151850
Suggested by: bde
Approved by: jhb (Mentor)
MFC after: 2 weeks
- Fix boot0 to check for PXE when using the pre-set setting for the
preferred slice.
- Update boot0cfg to use slice 6 to select PXE. Accept a 'pxe' argument
instead of a number for the 's' option as a way to select PXE as well.
Submitted by: Andrew Boyer aboyer averesystems
MFC after: 2 weeks
7.x, 8.x and 9.x with pf(4) imports: pfsync(4) should suppress CARP
preemption, while it is running its bulk update.
However, reimplement the feature in more elegant manner, that is
partially inspired by newer OpenBSD:
- Rename term "suppression" to "demotion", to match with OpenBSD.
- Keep a global demotion factor, that can be raised by several
conditions, for now these are:
- interface goes down
- carp(4) has problems with ip_output() or ip6_output()
- pfsync performs bulk update
- Unlike in OpenBSD the demotion factor isn't a counter, but
is actual value added to advskew. The adjustment values for
particular error conditions are also configurable, and their
defaults are maximum advskew value, so a single failure bumps
demotion to maximum. This is for POLA compatibility, and should
satisfy most users.
- Demotion factor is a writable sysctl, so user can do
foot shooting, if he desires to.
- Let panic() use _Noreturn and __printflike() instead of GCC-specific
attributes.
- Remove prototype from ffs_subr.c and let it include ffs_extern.h.
- Forward declare struct inode to make ffs_extern.h not depend on it.
* Right now the delay is hard coded at 10uS. This is a bit long when doing lots
of periodic i2c transactions. So create a 'udelay' parameter and initialise it
to 10. This can be tuned later.
* Add a newline after a transaction finishes, so the debugging output isn't so
horrible.
performance issues.
* Access to the GPIO bus is already locked by requesting
and releasing the bus - thus the lock isn't really needed
for each GPIO pin change.
* Don't lock and unlock the GPIO bus for -each- i2c access -
the i2c bus code is already doing this by calling the upper
layer callback to request/release the bus. This thus locks
the bus for the entirety of the transaction.
TODO:
* Further verify that everything is correctly requesting/
releasing the GPIO bus.
* Look at how to lock the GPIO pin configuration stuff,
potentially by locking/unlocking the bus at the gpiobus
layer.
With the previous code, if the range of priorities for timeshare batch
threads was greater than RQ_NQS, then the threads with low priorities in
the part of the range above RQ_NQS would be scheduled to the run-queues
as if they had high priorities at the beginning of the range.
In other words, threads with a nice level of +N could be scheduled as
if they had a nice level of -M.
Reported by: George Mitchell <george@m5p.com>
Reviewed by: jhb
Tested by: George Mitchell <george@m5p.com> (earlier version)
MFC after: 1 week
Fix the TCP header size calculation such that makes TSO engine
cache all header(ethernet/IP/TCP) bytes to its internal buffer.
While here, remove extra pull up for TCP payload. Unlike some
em(4) controllers, fxp(4) does not require such work around for
TSO.
The two limitations are ethernet/IP/TCP header size should be less
than or equal to the size of controller's internal buffer(80 bytes)
and these header information should be found in the first fragment
of a TSO frame.
- Cast time_t's to long, and print them with %ld.
- Print ptrdiff_t's with %td.
- Print ssize_t's and size_t's with %zd and %zu.
- Print int32_t's with %d.
Also, replace some int variables with the more appropriate size_t.
MFC after: 1 week
against icmp6_hdr::icmp6_type is done incorrectly. (This fix has
already been applied upstream, but we do not have the latest version of
tcpdump.)
MFC after: 1 week
of the rx_ring to bus_dmamap_sync(9). Given that netmap code tries to
obtain the bus addresses of netmap buffers via vtophys(9) instead of using
bus_dma(9) it currently has zero chance of actually working on sparc64
though (and for that matter f.e. also not with MACs limited to 32-bit DMA
on x86 machines with more than 4GB of RAM).
