3 Commits

Author	SHA1	Message	Date
Marius Strobl	3c7ae7bf67	Update for UltraSPARC-IV{,+} and SPARC64 V, VI, VII and VIIIfx CPUs.	2010-04-11 15:35:17 +00:00
Thomas Moestl	fe905bcb53	Add new LSU bits for UltraSPARC-III.	2002-07-16 16:24:03 +00:00
Jake Burkholder	076f1c081a	Add definitions for bits in condition code register and the load store ... unit control registers. Move tstate definitions to their own file. Submitted by: tmm	2001-08-20 23:34:46 +00:00