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18 Commits

Author SHA1 Message Date
Alexander Motin
cfa892b592 Add basic cpu_sleep() support for Marvell SoCs. This drops my SheevaPlug's 
heatsink termperature in open air from 49C to 43C when idle.
 2010-09-18 16:57:05 +00:00
Kevin Lo
64c68f1c50 Add support for FA626TE. 
Tested on GM8181 development board.
 2010-05-04 10:14:05 +00:00
Rui Paulo
381a19cce0 Add support for Cavium Econa CNS11XX ARM boards. These boards were 
previously know by StarSemi STR9104.

Tested by the submitter on an Emprex NSD-100 board.

Submitted by:	Yohanes Nugroho <yohanes at gmail.com>
Reviewed by:	freebsd-arm, stas
Obtained from:	//depot/projects/str91xx/...
 2010-01-04 03:35:45 +00:00
Rafal Jaworowski
1ee5b3b422 Fix confusing naming of Marvell ARM CPU specific routines. 
- The contents of 'feroceon_cpufuncs' dispatch table was really dedicated for the
  new Sheeva CPU (in 88F6xxx and MV-78xxx SOCs), and NOT Feroceon.

- Feroceon CPU (in 88F5xxx SOCs) appears as a regular ARM926EJ-S core and does
  not require dedicated routines.

This will be accompanied by a file rename commit.
 2009-01-09 10:45:04 +00:00
Rafal Jaworowski
ba6faad63c Introduce low-level support for new Marvell core CPUs: 88FR131, 88FR571. 
They are compliant with ARMv5TE and integrated on 88F6281 (Kirkwood) and
MV78100 (Discovery) system-on-chip families.

Obtained from:	Marvell, Semihalf
 2008-10-13 18:16:54 +00:00
Warner Losh
63b2597849 Merge support from p4 (from NetBSD) for arm9e and arm10, arm11 cores. Not 
yet connected to the build, but reduces diffs to p4 repo.

Obtained from: NetBSD
 2007-10-18 05:33:06 +00:00
Olivier Houchard
425b5be335 Add a new set of functions to handle L2 cache. Make them no-op for every 
CPU except Xscale core 3.

Approved by:	re (blanket)
 2007-07-27 14:39:41 +00:00
Kevin Lo
4eaa43e6f4 Remove __P 2007-03-21 03:28:16 +00:00
Olivier Houchard
676b1fbdbf Identify the xscale 81342. 2006-11-07 22:36:57 +00:00
Olivier Houchard
11d1528ce0 Finally bring it support for the i80219 XScale processor. 
Submitted by:	Max M. Boyarov <m.boyarov bsd by>
 2006-08-24 23:51:28 +00:00
Olivier Houchard
27b45ae819 Don't enable the FIQ in enable_interrupts() if F32_bit is not specified. 
This has been committed by mistake.

Reported by:	ssouhlal
 2006-06-01 16:17:44 +00:00
Olivier Houchard
094df9739b Bring in bits I forgot while importing write back support for arm9. 2005-06-03 19:49:53 +00:00
Warner Losh
d8315c79d9 Start all license statements with /*- 2005-01-05 21:58:49 +00:00
Olivier Houchard
3488a2f7d9 Implement enough to be able to enter and leave DDB. 2004-11-20 16:52:10 +00:00
Olivier Houchard
24e01b0c59 Use interrupts_disable() and interrupts_restore() as intr_disable() and 
intr_restore() instead of re-implement it.
 2004-11-04 19:18:50 +00:00
Olivier Houchard
be687a0dda Nuke disable_intr() and enable_intr(), as it already exists elsewhere. 2004-07-20 22:38:46 +00:00
Olivier Houchard
4628245baa Implement a stub breakpoint(). 2004-07-12 21:20:38 +00:00
Olivier Houchard
6fc729af63 Import FreeBSD/arm kernel bits. 
It only supports sa1110 (on simics) right now, but xscale support should come
soon.
Some of the initial work has been provided by :
Stephane Potvin <sepotvin at videotron.ca>
Most of this comes from NetBSD.
 2004-05-14 11:46:45 +00:00