Commit Graph

5 Commits

Author SHA1 Message Date
Rafal Jaworowski
c72ef339bf Adjust mvs(4) to handle interrupt cause reg depending on the actual number of
channels available

- current code treats bits 4:7 in 'SATAHC interrupt mask' and 'SATAHC
  interrupt cause' as flags for SATA channels 2 and 3

- for embedded SATA controllers (SoC) these bits have been marked as reserved
  in datasheets so far, but for some new and upcoming chips they are used for
  purposes other than SATA

Submitted by:	Lukasz Plachno
Reviewed by:	mav
Obtained from:	Semihalf
MFC after:	2 weeks
2012-02-01 13:39:52 +00:00
Alexander Motin
7bcc595738 Fix some English grammar. 2011-04-19 10:57:40 +00:00
Alexander Motin
70b7af2b21 Refactor hard-reset implementation in mvs(4).
Instead of spinning in a tight loop for up to 15 seconds, polling for device
readiness while it spins up, return reset completion just after PHY reports
"connect well" or 100ms connection timeout. If device was found, use callout
for checking device readiness with 100ms period up to full 31 second timeout.

This fixes system freeze for 5-10 seconds on drives hot plug-in.
2011-04-14 07:49:45 +00:00
Alexander Motin
97fd3ac63f Implement automatic SCSI sense fetching for mvs(4).
Make few improvements/changes to ATAPI PIO support to pass most of scgcheck
(cdrtools) tests.
2011-04-12 16:01:27 +00:00
Alexander Motin
dd48af360f Import mvs(4) - Marvell 88SX50XX/88SX60XX/88SX70XX/SoC SATA controllers
driver for CAM ATA subsystem. This driver supports same hardware as
atamarvell, ataadaptec and atamvsata drivers from ata(4), but provides
many additional features, such as NCQ, PMP, etc.
2010-05-02 19:28:30 +00:00