Commit Graph

3 Commits

Author SHA1 Message Date
Brooks Davis
3b05ffaf6f Replace SOFTFLOAT with __riscv_float_abi_*.
With SOFTFLOAT, libc and libm were built correctly, but any program
including fenv.h itself assumed it was on a hardfloat systen and emitted
inline fpu instructions for fedisableexcept() and friends.

Unlike r315424 which did this for MIPS, I've used riscv_float_abi_soft
and riscv_float_abi_double macros as appropriate rather than using
__riscv_float_abi_soft exclusively.  This ensures that attempts to use an
unsupported hardfloat ABI will fail.

Reviewed by:	br
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D10039
2018-04-19 20:36:15 +00:00
Ruslan Bukin
7804dd5212 Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D8529
2016-11-16 15:21:32 +00:00
Ruslan Bukin
4bf1032a04 Add fenv.c for RISC-V. Copied from MIPS. 2016-01-26 14:40:41 +00:00