2 Commits

Author	SHA1	Message	Date
Ian Lepore	a286c311ab	Add minimum cache line sizes to struct cpuinfo, use them in the new cache ... maintenance routines. Also add a routine to invalidate the branch cache. Submitted by: Michal Meloun	2015-03-09 14:46:10 +00:00
Ian Lepore	2b71562fd8	Add new code to read and parse cpu identification data using the new CPUID ... mechanism defined for armv7 (and also present on some armv6 chips including the arm1176 used on rpi). The information is parsed into a global cpuinfo structure, which will be used by (upcoming) new cache and tlb maintenance code to handle cpu-specific variations of the maintence sequences. Submitted by: Svatopluk Kraus <onwahe@gmail.com>, Michal Meloun <meloun@miracle.cz	2014-12-28 18:12:56 +00:00