Commit Graph

50 Commits

Author SHA1 Message Date
Ian Lepore
3f62727443 Move the DRIVER_MODULE() statements that declare mmc(4) to be a child of
the various bridge drivers out of dev/mmc.c and into the bridge drivers.

Requested by:	   jhb (almost two years ago; better late than never)
2015-12-14 01:09:25 +00:00
Adrian Chadd
93efdc635d Add support for the BCM57765 card reader.
This patch adds support for the BCM57765[2] card reader function included in
Broadcom's BCM57766 ethernet/sd3.0 controller. This controller is commonly
found in laptops and Apple hardware (MBP, iMac, etc).

The BCM57765 chipset is almost fully compatible with the SD3.0 spec, but
does not support deriving a frequency below 781KHz from its default base
clock via the standard SD3.0-configured 10-bit clock divisor.

If such a divisor is set, card identification (which requires a 400KHz
clock frequency) will time out[1].

As a work-around, I've made use of an undocumented device-specific clock
control register to switch the controller to a 63MHz clock source when
targeting clock speeds below 781KHz; the clock source is likewise switched
back to the 200MHz clock when targeting speeds greater than 781KHz.

Additionally, this patch fixes a small sdhci_pci bug; the
sdhci_pci_softc->quirks flag was not copied to the sdhci_slot, resulting in
`quirk` behavior not being applied by sdhci.c.

[1] A number of Linux/FreeBSD users have noted that bringing up the chipsets'
associated ethernet interface will allow SD cards to enumerate (slowly).
This is a controller implementation side-effect triggered by the ethernet
driver's reading of the hardware statistics registers.

[2] This may also fix card detection when using the BCM57785 chipset, but I
don't have access to the BCM57785 chipset and can't verify.

I actually snagged some BCM57785 hardware recently (2012 Retina MacBook Pro)
and can confirm that this also fixes card enumeration with the BCM57785
chipset; with the patch, I can boot off of the internal sdcard reader.

PR:		kern/203385
Submitted by:	Landon Fuller <landon@landonf.org>
2015-10-15 04:22:56 +00:00
Luiz Otavio O Souza
ba6fc1c73c Raise the SDHCI timeout to 10 seconds and add a sysctl to allow changing
this value at runtime.

The SD card specification says that a block write or a block erase can take
up to 250ms to complete and thus, under some circumstances, the existent 2
seconds timeout was triggering with normal usage.

This change fixes the sporadic controller timeout that happens on RPi and
RPi 2.

Discussed with:		ian (some time ago)
2015-05-21 20:09:36 +00:00
Ian Lepore
2d1731b857 Detect, report and use 8-bit bus if is available.
Differential Revision:	https://reviews.freebsd.org/D1921
Submitted by:	Michal Meloun
2015-02-27 15:47:30 +00:00
Ian Lepore
bba987dc50 Add a new SDHCI quirk, SDHCI_QUIRK_DONT_SET_HISPD_BIT. Apparently some
sdhci controllers, such as the one on a Raspberry Pi, mishandle the signal
timing in high speed signaling mode, but run just fine in standard mode
with the bus running at frequencies between 25-50MHz (which shouldn't work).

This is the solution adopted by U-Boot and other OSes (linux and *BSD)
for the timeouts on Raspberry Pi boards with certain SD cards.  Some
research shows that this quirk is also used on a few other boards, so the
fix is a generic quirk instead of being in the RPi-specific driver code.

This change is based on information discovered by Michal Meloun.
2015-01-17 19:57:03 +00:00
Ian Lepore
cf5bb7ca1c Add defines for SDHCI 3.0 controllers.
Submitted by:	Michal Meloun <meloun@miracle.cz>
2015-01-17 18:56:22 +00:00
Ian Lepore
a98788edff Handle the possibility that SDHCI_PLATFORM_START_TRANSFER() can fail, by
moving the handling of curcmd->error != 0 to the end of the interrupt
handler.  Also make sdhci_finish_data() idempotent by moving the setting
of slot->data_done = 1 down past the point where the busdma buffer is
unmapped.  This allows for the possibility that the finish routine can
get called from multiple places when handling errors.
2015-01-11 21:25:03 +00:00
Marius Strobl
c22626471e - Switching the mode of Ricoh R5CE823 to SD2.0 causes their PCI device ID
to change to 0xe822, which may be persistent across reboots and, thus,
  confuse other OSes. Therefore, restore the original mode and frequency
  setting on detach and shutdown.
- Report Ricoh R5CE822 as such.
- According to Linux, Ricoh R5CE822 also need SDHCI_QUIRK_LOWER_FREQUENCY.
- Nuke an unused softc member.

MFC after:	3 days
2014-12-31 16:06:26 +00:00
Ian Lepore
61bc42f782 Add a new sdhci quirk, SDHCI_QUIRK_WAITFOR_RESET_ASSERTED, to work around
TI OMAP controllers which will return the reset-in-progress bit as zero if
you read the status register too fast after setting the reset bit.

The zero is apparently from a stale snapshot of the internal state presented
in the interface register, and leads to a false indication that the reset
is complete when it either hasn't started yet or is in-progress.  The
workaround is to first loop until the bit is seen as asserted, then do the
normal loop waiting to see it de-asserted.

Submitted by:	Michal Meloun <meloun@miracle.cz>
2014-12-20 01:13:13 +00:00
Ian Lepore
7e5866432f When command and data interrupts have been aggregated together, don't do
the data-completed processing if a command-error interrupt is also asserted.

Reviewed by:	Michal Meloun <meloun@miracle.cz>
2014-12-20 00:37:56 +00:00
Warner Losh
5df0ffc762 class, subclass and progif were never used, so don't bother setting
them.
2014-10-13 16:23:51 +00:00
Marius Strobl
f0d2731dd8 - Nuke unused sdhci_softc.
- Static'ize sdhci_debug local to sdhci.c.
- Const'ify PCI device description strings.
- Nuke redundant resource ID members from sdhci_pci_softc.
- Nuke unused hw.sdhci_pci.debug tunable.
- Add support for using MSI instead of INTx, controllable via the tunable
  hw.sdhci.enable_msi (defaulting to on) and tested with a RICOH R5CE823 SD
  controller.
- Use NULL instead of 0 for pointers.

MFC after:	3 days
2014-08-31 17:56:54 +00:00
Hans Petter Selasky
af3b2549c4 Pull in r267961 and r267973 again. Fix for issues reported will follow. 2014-06-28 03:56:17 +00:00
Glen Barber
37a107a407 Revert r267961, r267973:
These changes prevent sysctl(8) from returning proper output,
such as:

 1) no output from sysctl(8)
 2) erroneously returning ENOMEM with tools like truss(1)
    or uname(1)
 truss: can not get etype: Cannot allocate memory
2014-06-27 22:05:21 +00:00
Hans Petter Selasky
3da1cf1e88 Extend the meaning of the CTLFLAG_TUN flag to automatically check if
there is an environment variable which shall initialize the SYSCTL
during early boot. This works for all SYSCTL types both statically and
dynamically created ones, except for the SYSCTL NODE type and SYSCTLs
which belong to VNETs. A new flag, CTLFLAG_NOFETCH, has been added to
be used in the case a tunable sysctl has a custom initialisation
function allowing the sysctl to still be marked as a tunable. The
kernel SYSCTL API is mostly the same, with a few exceptions for some
special operations like iterating childrens of a static/extern SYSCTL
node. This operation should probably be made into a factored out
common macro, hence some device drivers use this. The reason for
changing the SYSCTL API was the need for a SYSCTL parent OID pointer
and not only the SYSCTL parent OID list pointer in order to quickly
generate the sysctl path. The motivation behind this patch is to avoid
parameter loading cludges inside the OFED driver subsystem. Instead of
adding special code to the OFED driver subsystem to post-load tunables
into dynamically created sysctls, we generalize this in the kernel.

Other changes:
- Corrected a possibly incorrect sysctl name from "hw.cbb.intr_mask"
to "hw.pcic.intr_mask".
- Removed redundant TUNABLE statements throughout the kernel.
- Some minor code rewrites in connection to removing not needed
TUNABLE statements.
- Added a missing SYSCTL_DECL().
- Wrapped two very long lines.
- Avoid malloc()/free() inside sysctl string handling, in case it is
called to initialize a sysctl from a tunable, hence malloc()/free() is
not ready when sysctls from the sysctl dataset are registered.
- Bumped FreeBSD version to indicate SYSCTL API change.

MFC after:	2 weeks
Sponsored by:	Mellanox Technologies
2014-06-27 16:33:43 +00:00
Ian Lepore
e625c10b2f Honor the max-frequency property if it appears in the fdt data.
Adjust the exynos and zedboard dts files to use max-frequency (the
documented standard property) instead of clock-frequency.

Submitted by:	Thomas Skibo <ThomasSkibo@sbcglobal.net>
2014-05-02 01:28:19 +00:00
Ian Lepore
4ddc017276 When changing the sd bus clock divisor, clear just the bus clock enable bit
before changing the divisor bits in the register.  We were writing a zero
to the register, which clears the enable, but also cleared the divisor bits
at the same time.  That's a violation of the sdhci spec, which says the
divisor can only be changed when the clock is disabled.  This has worked
okay on most hardware for years, but the TI OMAP controller would misbehave
after changing the divisor improperly.

Submitted by:	Svatopluk Kraus <onwahe@gmail.com>
2014-04-04 01:10:02 +00:00
Ian Lepore
a6873fd141 After a timeout, reset the controller using SDHCI_RESET_CMD|SDHCI_RESET_DATA
rather than SDHCI_RESET_ALL; the latter turns off clocks and power, removing
any possibility of recovering from the error.

Also, double the timeout to 2 seconds.  Despite what the SD spec says about
all transactions completing in 250ms or less, I have a card which sometimes
takes more than a second to complete a write.
2014-02-16 17:22:49 +00:00
Ian Lepore
e64f01a94a Add timeout logic to sdhci, separate from the timeouts done by the hardware.
If the hardware is not in a good state (like maybe clocks aren't running
because of a configuration glitch) its timeout clock may also not work
correctly, and the next command sent will hang that thread forever.  The
thread in question is usually the one and only thread (at init time) or
a bio queue worker thread whose lockup will eventually lead to the whole
system locking up when it runs out of buffers.

No sd card command should take longer than 250ms.  This new code establishes
a 1-second timeout to allow plenty of safety margin over that.
2014-02-15 20:45:53 +00:00
Ian Lepore
8775ab4589 Increase the wait time for acquiring the bus from 10 to 250ms.
Normally it never needs to wait here at all; waiting is done at the end
of the prior command.  When doing a crash dump, the normal interrupt
mechanism isn't used; instead the interrupt handler is called repeatedly
in a polling-like manner.  This can subvert hardware-specific drivers
and lead to trying to start a new command while the previous command is
still busy on the bus.  Since the SD spec says the longest a card can
take to execute any command is 250ms, use that as a timeout.
2014-02-15 17:59:32 +00:00
Ian Lepore
4c155ae194 Fix the definition of the SDHCI_STATE_DAT and SDHCI_STATE_CMD fields, and
add SDHCI_RETUNE_REQUEST.  None of these are actually used in the code yet.
2014-02-12 22:25:08 +00:00
Ian Lepore
add35ed5b8 Follow r261352 by updating all drivers which are children of simplebus
to check the status property in their probe routines.

Simplebus used to only instantiate its children whose status="okay"
but that was improper behavior, fixed in r261352.  Now that it doesn't
check anymore and probes all its children; the children all have to
do the check because really only the children know how to properly
interpret their status property strings.

Right now all existing drivers only understand "okay" versus something-
that's-not-okay, so they all use the new ofw_bus_status_okay() helper.
2014-02-02 19:17:28 +00:00
Rui Paulo
ecc2d99765 Style changes and typos fixed. 2013-08-19 05:48:42 +00:00
Ian Lepore
87a6a871e2 Allow a hardware driver to pass clock frequencies into the sdhci driver.
The sdhci spec says that if the base or timeout clock frequency in the
capabilities register is zero, the driver must obtain the frequency "from
another source."  This change defines that other source to be the low-level
hardware driver, which can pre-set the frequencies in slot.max_clk and
slot.timeout_clk before calling sdhci_init_slot().

This helps with a growing number of SoCs that have sdhci base clock
frequencies that either won't fit into the range allowed by the number of
bits available in the capabilities register, or the frequency is runtime-
configurable.
2013-08-19 01:29:13 +00:00
Ian Lepore
677ee4943a Add a new SDHCI_QUIRK_DONT_SHIFT_RESPONSE for hardware that pre-shifts
the response bits the way we do in software.  While the hardware is just
doing the sensible thing rather than leaving it to the software, it's in
violation of the spec by doing so.  Grrrr.
2013-08-18 19:08:53 +00:00
Ian Lepore
54c665855d Add named constants for 8-bit bus support. The sdhci and mmc drivers
don't have support for this yet, but some low-level hardware is ready
for it when the higher layers catch up.
2013-08-16 19:44:49 +00:00
Ian Lepore
ceb9e9f70d When the timeout clock is based on the SD clock, the timeout counter
has to be recalculated every time the SD clock frequency changes.

Also, tidy up the counter calculation... it makes no sense to calculate
a value one larger than the limit, then whine that it's too large and
truncate it to the limit.  If the BROKEN_TIMEOUT quirk is set, don't
calculate the counter at all, just set it to the limit value.
2013-08-16 19:40:00 +00:00
Wojciech A. Koszek
a9caca6a75 Add Xilinx Zynq ARM/FPGA SoC support to FreeBSD/arm port.
Submitted by:	Thomas Skibo <ThomasSkibo (at) sbcglobal.net>
Reviewed by:	wkoszek, freebsd-arm@ (no objections raised)
2013-04-27 22:38:29 +00:00
Oleksandr Tymoshenko
c3a0f75a9f Add hooks for plugging platform-provided transfer backend.
In order to use platorm backend hardware driver should
impement three methods:
- platform_start_transfer and platform_finish_transfer
    to start and finish transfer
- platform_will_handle - check whether transaction is
    suitable for backend. If not - driver will fall back
    to PIO mode.

Submitted by:	Daisuke Aoyama <aoyama at peach.ne.jp>
Approved by:	ian@
2013-02-28 19:43:14 +00:00
Oleksandr Tymoshenko
acbaa69f31 Remove accidentally committed debug panic(9) call 2013-02-17 01:34:25 +00:00
Oleksandr Tymoshenko
7337a22fb0 Disable debug accidentally enabled by previous commit 2013-02-16 23:52:14 +00:00
Oleksandr Tymoshenko
57677a3a4a Various timing-related fixes:
- Replace divisor numbers with more descirptive names
- Properly calculate minimum frequency for SDHCI 3.0
- Properly calculate frequency for SDHCI 3.0 in mmcbr_set_clock
- Add min_freq method to sdhci_if.m and provide default
  implementation.  By re-implementing this method hardware
  drivers can control frequency controller operates when
  executing initialization sequence
2013-02-16 23:12:06 +00:00
Sofian Brabez
61bfd86762 Use DEVMETHOD_END macro defined in sys/bus.h instead of {0, 0} sentinel on device_method_t arrays
Reviewed by:	cognet
Approved by:	cognet
2013-01-30 18:01:20 +00:00
Oleksandr Tymoshenko
33aad34de6 - Get proper maximum clock frequency for SDHCI v3.0 and higher 2012-11-30 02:35:13 +00:00
Oleksandr Tymoshenko
8f3b7d5616 Add new quirks:
- Data timeout is broken
  - Data timeout uses SD clock
  - Capabilities register is unavailable

Add calculations for clock divisor for SDHCI 3.0
2012-10-29 17:21:58 +00:00
Oleksandr Tymoshenko
d6b3aaf842 Split sdhci driver in two parts: sdhci and sdhci_pci.
sdchi encapsulates a generic SD Host Controller logic that relies on
actual hardware driver for register access.

sdhci_pci implements driver for PCI SDHC controllers using new SDHCI
interface

No kernel config modifications are required, but if you load sdhc
as a module you must switch to sdhci_pci instead.
2012-10-16 01:10:43 +00:00
Gleb Smirnoff
ba32fa9394 Return back double spacing. 2012-07-30 08:56:56 +00:00
Gleb Smirnoff
1fc2ea61bf Fix typo in comment, should be MHz here.
Submitted by:	Daan Vreeken <Daan vitsch.nl>
2012-07-21 14:07:43 +00:00
Gleb Smirnoff
14d060a6b8 Add support for RICOH R5CE823 card reader, that can be found in
some Lenovo laptops.

The conroller needs a quirk to lower its frequency, and after
that it operates normally.
2012-02-09 10:20:41 +00:00
Ed Schouten
6472ac3d8a Mark all SYSCTL_NODEs static that have no corresponding SYSCTL_DECLs.
The SYSCTL_NODE macro defines a list that stores all child-elements of
that node. If there's no SYSCTL_DECL macro anywhere else, there's no
reason why it shouldn't be static.
2011-11-07 15:43:11 +00:00
Jayachandran C.
bcd91d25da Fix read_ivar implementation for MMC and SD.
1. Both mmc_read_ivar() and sdhci_read_ivar() use the expression
'*(int *)result = val' to assign to result which is uintptr_t *.
This does not work on big-endian 64 bit systems.

2. The media_size ivar is declared as 'off_t' which does not fit
into uintptr_t in 32bit systems, change this to long.

Submitted by:	kanthms at netlogicmicro com (initial version)
2011-05-30 06:23:51 +00:00
Pawel Jakub Dawidek
8bfafab1d2 Force DMA for controller found in Lenovo T510 (probably in others too).
This makes reads 10 times faster.

Discussed with:	mav
2011-02-27 13:58:20 +00:00
Alexander Motin
bea2dca299 Add support for interruptless kernel dumping. 2009-02-17 19:12:15 +00:00
Warner Losh
507a69a927 Fix read_ivar prototype. 2009-02-10 23:13:48 +00:00
Alexander Motin
5b69a497e5 Add hw.sdhci.debug sysctl to control debug level. 2009-01-28 22:53:41 +00:00
Alexander Motin
d493985afd Cleanup msleep() arguments.
Move wakeup() out of the lock.
2008-12-06 21:52:32 +00:00
Alexander Motin
d8208d9eb1 Forget current bus power settings on full reset. Chip must be reconfigured.
Do not issue command if there is no card, clock or power.
Controller will not detect command timeout without clock active.
2008-12-06 01:31:07 +00:00
Alexander Motin
92bf0e27a0 Add controller suspend/resume support.
To be able to correctly suspend/resume with card inserted,
respective support should be also implemented at mmc and mmcsd layers.
2008-12-01 17:45:56 +00:00
Alexander Motin
3a4a255741 Allow card reader bridge driver to report maximum supported transfer size.
sdhci supports up to 65535 blocks transfers, at91_mci - one block.

Enable multiblock operations disabled before to follow at91_mci driver
limitations.

Reviewed by:	imp@
2008-10-29 20:01:26 +00:00
Alexander Motin
831f5dcf12 Import sdhci (PCI SD Host Controller) driver.
Driver supports PCI devices with class 8 and subclass 5 according to
SD Host Controller Specification.

Update NOTES, enable module and static build.
Enable related mmc and mmcsd modules build.

Discussed on:   mobile@, current@
2008-10-21 20:33:40 +00:00