Commit Graph

144 Commits

Author SHA1 Message Date
Nathan Whitehorn
eaef5f0af8 Provide for multiple, cascaded PICs on PowerPC systems, and extend the
OFW interrupt map interface to also return the device's interrupt parent.

MFC after:	8.1-RELEASE
2010-06-18 14:06:27 +00:00
Marius Strobl
3eb0900b32 - Enable DMA write parity error interrupts on Schizo with a working
implementation.
- Revert the Sun Fire V890 WAR of r205254. Instead let schizo_pci_bus()
  only panic in case of fatal errors as the interrupt triggered by the
  error the firmware of these and also Sun Fire 280R with version 7
  Schizo caused may happen as late as using the HBA and not only prior
  to touching the PCI bus (in the former case the actual error still is
  fatal but we clear it before touching the PCI bus).
  While at it count and export non-fatal error interrupts via sysctl(9).
- Remove unnecessary locking from schizo_ue().
2010-05-14 20:00:21 +00:00
Marius Strobl
89fcb8cfa7 Add missing copyright shebang. 2010-04-10 12:10:11 +00:00
Marius Strobl
d5dba21cf6 Add sbbc(4), a driver for the BootBus controller found in Serengeti and
StarCat systems which provides time-of-day services for both as well as
console service for Serengeti, i.e. Sun Fire V1280. While the latter is
described with a device type of serial in the OFW device tree, it isn't
actually an UART. Nevertheless the console service is handled by uart(4)
as this allowed to re-use quite a bit of MD and MI code. Actually, this
idea is stolen from Linux which interfaces the sun4v hypervisor console
with the Linux counterpart of uart(4).
2010-04-10 11:52:12 +00:00
Marius Strobl
d7a0fc4dca Use device_get_nameunit(9) rather than device_get_name(9) so one can
identify the reporting bridge in machines with multiple PCI domains.
2010-03-31 22:32:56 +00:00
Marius Strobl
789a702ad3 Don't re-implement device_get_nameunit(9). 2010-03-31 22:27:33 +00:00
Marius Strobl
4a717bcedc - Take advantage of the INTCLR_* macros.
- Right-justify the backslashes as per style(9).
2010-03-31 22:19:00 +00:00
Marius Strobl
cb2f0c8ce1 - Add quirk handling for Sun Fire V1280. The firmware of these machines
provides no ino-bitmap properties so forge them using the default set
  of controller interrupts and let schizo_setup_intr() take care of the
  children, hoping for non-fancy routing.
- Add quirk handling for Sun Fire V890. When booting these machines from
  disk a Schizo comes up with PCI error residing which triggers as soon
  as we register schizo_pci_bus() even when clearing it from all involved
  registers (it's no longer indicated once we're in schizo_pci_bus()
  though). Thus make PCI bus errors non-fatal until we actually touch the
  bus. With this change schizo_pci_bus() typically triggers once during
  attach in this case. Obviously this approach isn't exactly race free
  but it's about the best we can do about this problem as we're not
  guaranteed that the interrupt will actually trigger on V890 either, as
  it certainly doesn't when for example netbooting them.
2010-03-17 20:01:01 +00:00
Marius Strobl
376a67cf64 - Zero the MSI/MSI-X queue argument, otherwise mtx_init(9) can panic
indicating an already initialized lock.
- Check for an empty MSI/MSI-X queue entry before asserting that we have
  received a MSI/MSI-X message in order to not panic in case of stray MSI/
  MSI-X queue interrupts which may happen in case of using an interrupt
  handler rather than a filter.

MFC after:	3 days
2010-01-27 20:30:14 +00:00
Marius Strobl
b10fd7e9cc When setting up MSIs with a filter ensure that the event queue interrupt
is cleared as it might have triggered before and given we supply NULL
as ic_clear, inthand_add() won't do this for us in this case.
2010-01-10 18:39:29 +00:00
Marius Strobl
0e34fcfba8 - According to OpenSolaris it's sufficient to align the MSIs of a
device in the table based on the count rather than the maxcount.
  Also the previous code didn't work properly as it would have been
  necessary to reserve the entire maxcount range in order keep later
  requests from filling the spare MSIs between count and maxcount,
  which would be complicated to unreserve in fire_release_msi().
- For MSIs with filters rather than handlers only don't clear the
  event queue interrupt via fire_intr_clear() since given that these
  are executed directly would clear it while we're still processing
  the event queue, which in turn would lead to lost MSIs.
- Save one level of indentation in fire_setup_intr().
- Correct a bug in fire_teardown_intr() which prevented it from
  correctly restoring the MSI in the resource, causing allocation of
  a resource representing an MSI to fail after the first pass when
  repeatedly loading and unloading a driver module.
2010-01-10 15:12:15 +00:00
Marius Strobl
c936816f6d - Preserve the PROM IOMMU in order to allow OFW drivers to continue to
work.
- Sanity check the parameters passed to the implementations of the
  pcib_{read,write}_config() methods. Using illegal values can cause
  no real harm but it doesn't hurt to avoid unnecessary data error
  traps requiring to flush and re-enable the level 1 caches.
2010-01-02 15:19:33 +00:00
Marius Strobl
c64b2eba8a - Remove a redundant variable and an unnecessary cast.
- Fix whitespace.
2009-12-29 14:06:36 +00:00
Marius Strobl
7d027c4ff2 - Prefer i and j over i and n for temporary integer variables.
- Wrap/shorten too long lines.
- Remove a redundant variable and an unnecessary cast in schizo(4).
2009-12-29 14:03:38 +00:00
Marius Strobl
4c6587a6cf Account for firmware versions which include the CDMA interrupts in
the OFW device tree.

MFC after:	3 days
2009-12-28 14:16:40 +00:00
Marius Strobl
5cb5104246 Add a driver for the `Fire' JBus to PCIe bridges found in at least
the Sun Fire V215/V245 and Sun Ultra 25/45 machines. This driver also
already includes all the code to support the `Oberon' Uranus to PCIe
bridges found in the Fujitsu-Siemens based Mx000 machines but due to
lack of access to such a system for testing, probing of these bridges
is currently disabled.
Unfortunately, the event queue mechanism of these bridges for MSIs/
MSI-Xs matches our current MD and MI interrupt frameworks like square
pegs fit into round holes so for now we are generous and use one event
queue per MSI, which limits us to 35 MSIs/MSI-Xs per Host-PCIe-bridge
(we use one event queue for the PCIe error messages). This seems
tolerable as long as most devices just use one MSI/MSI-X anyway.
Adding knowledge about MSIs/MSI-Xs to the MD interrupt code should
allow us to decouple the 1:1 mapping at the cost of no longer being
able to bind MSIs/MSI-Xs to specific CPUs as we currently have no
reliable way to quiesce a device during the transition of its MSIs/
MSI-Xs to another event queue. This would still require the problem
of interrupt storms generated by devices which have no one-shot
behavior or can't/don't mask interrupts while the filter/handler is
executed (like the older PCIe NICs supported by bge(4)) to be solved
though.

Committed from:	26C3
2009-12-27 16:55:44 +00:00
Marius Strobl
10a290af39 - Hook up the default implementations of the MSI/MSI-X pcib_if methods
so requests may bubble up to a host-PCI bridge driver.
- Distinguish between PCI and PCIe bridges in the device description
  so it's a bit easier to follow what hangs off of what in the dmesg.
  Unfortunately we can't also tell PCI and PCI-X apart based on the
  information provided in the OFW device tree.
- Add quirk handling for the ALi M5249 found in Fire-based machines
  which are used as a PCIe-PCIe bridge there. These are obviously
  subtractive decoding as as they have a PCI-ISA bridge on their
  secondary side (and likewise don't include the ISA I/O range in
  their bridge decode) but don't indicate this via the class code.
  Given that this quirk isn't likely to apply to all ALi M5249 and
  I have no datasheet for these chips so I could implement a check
  using the chip specific bits enabling subtractive decoding this
  quirk handling is added to the MD code rather than the MI one.
2009-12-25 15:03:05 +00:00
Marius Strobl
3438bdc53e Merge from amd64/i386:
Implement support for interrupt descriptions.
2009-12-24 15:43:37 +00:00
Marius Strobl
926f4e43c6 - Add quirk handling for ALi M5229, mainly setting the magic "force
enable IDE I/O" bit which prevents data access traps with revision
  0xc8 in Fire-based machines when pci(4) enables PCIM_CMD_PORTEN.
- Like for sun4v also don't add the PCI side of host-PCIe bridges to
  the bus on sun4u as they don't have configuration space implement
  there either.
2009-12-23 21:38:59 +00:00
Marius Strobl
9cc21da577 - Sort the prototypes.
- Add macros to ease the access of device configuration space in
  ofw_pcibus_setup_device().
2009-12-23 21:25:16 +00:00
Marius Strobl
36fd650f09 Add structures for OFW MSI/MSI-X support. These are identical for
both sun4u and sun4v.
2009-12-23 21:07:49 +00:00
Marius Strobl
1bba41a506 Enroll these drivers in multipass probing. The motivation behind this
is that the JBus to EBus bridges share the interrupt controller of a
sibling JBus to PCIe bridge (at least as far as the OFW device tree
is concerned, in reality they are part of the same chip) so we have to
probe and attach the latter first. That happens to be also the case
due to the fact that the JBus to PCIe bridges appear first in the OFW
device tree but it doesn't hurt to ensure the right order.
2009-12-22 21:02:46 +00:00
Marius Strobl
75b02cac5a Provide and consume missing module dependency information. 2009-12-21 21:29:16 +00:00
Marius Strobl
7b8253c3eb Factor out the duplicated macro for the device type used in the
OFW device tree for PCI bridges and add a new one for PCI Express.
While at it, take advantage of the former for the rman(9) work-
around in jbusppm(4).
2009-09-13 14:47:31 +00:00
Marius Strobl
45091a0b8c Bring the implementation of the pnpinfo string function more in
line with the rest of this file.
2009-03-19 21:12:44 +00:00
Marius Strobl
2ba16c40b4 - Ensure we find no unexpected partner.
- Failing to register as interrupt controller during attach shouldn't
  be fatal so just inform about this instead of panicing.
- Disable rerun of the streaming cache as workaround for a silicon bug
  of certain Psycho versions.
- Remove the comment regarding lack of newbus'ified bus_dma(9) as being
  able to associate a DMA tag with a device would allow to implement
  CDMA flushing/syncing in bus_dmamap_sync(9) but that would totally
  kill performance. Given that for devices not behind a PCI-PCI bridge
  the host-to-PCI bridges also only do CDMA flushing/syncing based on
  interrupts there's no additional disadvantage for polling(4) callbacks
  in the case schizo(4) has to do the CDMA flushing/syncing but rather a
  general problem.
- Don't panic if the power failure, power management or over-temperature
  interrupts doesn't exist as these aren't mandatory and not available
  with all controllers (not even Psychos). [1]
- Take advantage of KOBJMETHOD_END.
- Remove some redundant variables.
- Add missing const.

PR:	131371 [1]
2009-03-19 20:52:46 +00:00
Marius Strobl
d7ae285095 - Take advantage of KOBJMETHOD_END.
- Hook up the streaming buffer (not used by iommu(4) by default, yet)
  if available and usable. [1]
- Move the message regarding belated registration as interrupt control
  under bootverbose as this isn't something the user should worry about.

Tested by:	Michael Moll [1]
2009-03-19 20:48:47 +00:00
Marius Strobl
eea83874d9 Take advantage of KOBJMETHOD_END. 2009-03-19 20:36:46 +00:00
Marius Strobl
b66196f2e9 - Sort device methods.
- Take advantage of KOBJMETHOD_END.
2009-03-19 20:31:55 +00:00
Marius Strobl
5773d864f9 - Failing to register as interrupt controller during attach shouldn't
be fatal so just inform about this instead of panicing.
- Ensure we use the right softc in case the interrupt of a child is
  is routed to the companion PBM instead. This hasn't been seen in the
  wild so far but given that it's the case for the Schizo interrupts,
  handling this situation also for child interrupts as a precaution
  seemed a good idea.
- Deal with broken firmware versions which miss child entries in the
  ino-bitmap as seen on V880 by belatedly registering as interrupt
  controller in schizo_setup_intr(). [1]
- Add missing '\n' when printing the warning regarding Schizo Errata
  I-13.

Reported and tested by:	Beat Gaetzi [1]
2008-12-18 18:29:15 +00:00
Nathan Whitehorn
94b4a038a1 Adapt parts of the sparc64 Open Firmware bus enumeration code (in particular,
the code for parsing interrupt maps) to PowerPC and reflect their new MI
status by moving them to the shared dev/ofw directory.

This commit also modifies the OFW PCI enumeration procedure on PowerPC to
allow the bus to find non-firmware-enumerated devices that Apple likes to add,
and adds some useful Open Firmware properties (compat and name) to the pnpinfo
string of children on OFW SBus, EBus, PCI, and MacIO links. Because of the
change to PCI enumeration on PowerPC, X has started working again on PPC
machines with Grackle hostbridges.

Reviewed by:	marius
Obtained from:	sparc64
2008-12-15 15:31:10 +00:00
Marius Strobl
1191b0a44b - According to OpenSolaris, CDMA flushing/syncing for Tomatillos
and XMITS has to be basically done in the same manner as for
  the Sabres, i.e. only for devices behind PCI-PCI-bridges and
  after a PIO read on the far side of the farest PCI-PCI-bridge.
  Given that the Tomatillo documentation mentions no difference
  to the Schizo bridges in this regard and this is also still
  part of the procedure described Schizo documentation this
  seems about right so adjust accordingly (the unconditional
  CDMA flushing/syncing previously done was based on how Linux
  behaves).
- Implement CDMA flushing/syncing for Schizo version >= 5,
  which requires the workaround described in Schizo Errata I-23.
  According to Schizo Errata I-13 it's just unusable with
  version < 5 though. [1]
- Don't register the Schizo streaming buffer for now until it's
  usage is sorted out according to the erratas.
- Register our interrupt filters with the revived INTR_FAST so
  they these interrupts can even interrupt filters of device
  drivers as necessary.
- Remove the comment regarding lack of newbus'ified bus_dma(9)
  as being able to associate a DMA tag with a device would
  allow to implement CDMA flushing/syncing in bus_dmamap_sync(9)
  but that would totally kill performance. Given that for devices
  not behind a PCI-PCI bridge the host-to-PCI bridges also only
  do CDMA flushing/syncing based on interrupts there's no
  additional disadvantage for polling(4) callbacks in the case
  schizo(4) has to do the CDMA flushing/syncing but rather a
  general problem.

Reported by:	Michael Moll [1]
2008-11-20 18:44:09 +00:00
Marius Strobl
b08a33129a - Turn off interrupts instead of only entering a critical section
while doing the block store workaround so we restore the correct
  floating-point registers state in case of nested floating-point
  operations resulting from nested interrupts. This allows the
  VIS-based block copy/zero functions to be used on machines
  requiring this workaround. Alternatively, we could take care of
  saving the floating-point registers here, which would be more
  inefficiently though and also involves turning off interrupts.
- It turns out that the SCZ_PCI_DMA_SYNC register doesn't work
  like the TOMXMS_PCI_DMA_SYNC_PEND one (but more like the
  corresponding register in of Hummingbird and Sabre bridges)
  and writing the INO of the respective device to it causes a
  Safari bus error. However, due to the Schizo errata I-23,
  SCZ_PCI_DMA_SYNC can't be used as intended either, so remove
  consistent DMA syncing for Schzio bridges for now, which means
  that add-on cards with non-"sun4u compliant" (whatever that
  means exactly) PCI-PCI-bridges should be avoided until the
  proper workaround is implemented. [1]

Reported by:	Michael Moll [1]
2008-10-28 22:05:20 +00:00
Marius Strobl
20284fcdd9 Add a driver for Schizo' Fireplane/Safari to PCI 2.1 and Tomatillo'
JBus to PCI 2.2 bridges. In theory, this driver should also handle
`XMITS' Fireplane/Safari to PCI-X bridges but due to lack of access
to such hardware, support for these hasn't be fleshed out, yet.
2008-09-28 00:07:05 +00:00
Marius Strobl
9d769eb369 Clear any possibly pending PCI error bits left by the firmware. These
could trigger an error interrupt that we can't actually to do anything
against as soon as enabling the error handlers.
While at it don't bother about writing only to the write-one-to-clear
bits when clearing error bits.
2008-09-18 19:45:22 +00:00
Marius Strobl
bdebc2daa5 Announce the speed of the PCI bus for informational purpose.
MFC after:	3 days
2008-08-24 16:22:04 +00:00
Marius Strobl
c87ba3b18c The PCI specifications don't explain the details on how to calculate
the latency based on the Min_Gnt register so use the algorithm found
in OpenSolaris as they probably know how to interpret the value Sun
puts into these registers (previously, the latency calculated for
66MHz was most likely wrong) and for bridges additionally set up the
secondary latency register. Also set up the bridge control register
the way it's done in OpenSolaris. As the latency register don't apply
to PCI-Express and the bridge control setup wasn't tested on sun4v
(besides most likely not being needed), expand the #ifndef SUN4V
accordingly.

MFC after:	3 days
2008-08-24 15:05:46 +00:00
Marius Strobl
898112a7dc cosmetic changes and style fixes 2008-08-22 20:28:19 +00:00
Marius Strobl
083b2bd41a - Use the name returned by device_get_nameunit(9) for the name of the
counter-timer timecounter so the associated SYSCTL nodes don't clash on
  machines having multiple U2P and U2S bridges as well as establishing a
  clear mapping between these bridges and their timecounter device.
- Don't bother setting up a "nice" name for the IOMMU, just use the name
  returned by device_get_nameunit(9), too.
- Fix some minor style(9) bugs.
- Use __FBSDID in counter.c

MFC after:	1 week
2008-05-07 21:22:15 +00:00
Marius Strobl
0b5a77c6a4 Remove an header which is unused for sun4v.
MFC after:	3 days
2008-05-02 17:44:18 +00:00
Marius Strobl
b7ee09f7b0 Remove the MD isa_irq_pending() and the underlying PCI-specific
infrastructure. Its only consumer ever was sio(4) and thus was
unused on sparc64 since removing the last traces of sio(4) in
sparc64 configuration files in favor for uart(4) over three
years ago. If similar functionality is required again it should
be brought back as an MD intr_pending() which works for all
busses by using for example interrupt controller hooks.
2008-04-26 11:01:38 +00:00
Marius Strobl
526bd70425 o Rename ic_eoi to ic_clear to emphasize the functions it points
don't send and EOI which works like on amd64/i386 and blocks all
  interrupts on the relevant interrupt controller.
o Replace the post_filter and post_inthread hooks registered when
  creating the interrupt events with just ic_clear as on sparc64 we
  don't need to do any disable->EOI->enable dance to unblock all but
  the relevant interrupt while running the filter or handler; just
  not clearing the interrupt already has the same effect.
o Merge from amd64/i386:
  - Split the intr_table_lock into an sx lock used for most things,
    and a spin lock to protect intrcnt_index.
  - Add support for binding interrupts to CPUs, including for the
    bus_bind_intr(9) interface, a assign_cpu hook and initially
    shuffling interrupts arround in a round-robin fashion.

Reviewed by:	jhb
MFC after:	1 month
2008-04-23 20:04:38 +00:00
Marius Strobl
9d9a12b8d1 On sparc64 machines with multiple host-PCI-bridges these bridges
have separate configuration spaces so by definition they implement
different PCI domains. Thus change psycho(4) to use PCI domains
instead of reenumerating all PCI busses so they have globally unique
bus numbers and drop support for reenumerating busses in the OFW PCI
code.
According to CVS history reenumeration was also required in order to
get some E450 to boot but given that no other open source kernel
changes the PCI bus numbers assigned by the firmware I believe the
real problem was that the old code used the bus number as the device
number for the PCI busses and unlike most of the other machines the
firmwares of the problematic ones don't use disjoint PCI bus numbers
across the host-PCI-bridges.

MFC after:	1 month
2008-04-17 12:38:00 +00:00
Robert Watson
3de213cc00 Add a new 'why' argument to kdb_enter(), and a set of constants to use
for that argument.  This will allow DDB to detect the broad category of
reason why the debugger has been entered, which it can use for the
purposes of deciding which DDB script to run.

Assign approximate why values to all current consumers of the
kdb_enter() interface.
2007-12-25 17:52:02 +00:00
Marius Strobl
ddcde502eb Fix a non-fatal off-by-one error in the previous revision. 2007-12-01 19:42:33 +00:00
Marius Strobl
9c13c513ad - Add the PCI side of the HOST-PCI bridge itself to the bus. This
is required by the X.Org PCI domains code and additionally needs
  a workaround for Hummingbird and Sabre bridges as these don't
  allow their config headers to be read at any width, which is an
  unusual behavior.
- In psycho(4) take advantage of DEFINE_CLASS_0 and use more
  appropriate types for some softc members.

MFC after:	3 days
2007-11-30 23:02:42 +00:00
Marius Strobl
55aaf894e8 Make the PCI code aware of PCI domains (aka PCI segments) so we can
support machines having multiple independently numbered PCI domains
and don't support reenumeration without ambiguity amongst the
devices as seen by the OS and represented by PCI location strings.
This includes introducing a function pci_find_dbsf(9) which works
like pci_find_bsf(9) but additionally takes a domain number argument
and limiting pci_find_bsf(9) to only search devices in domain 0 (the
only domain in single-domain systems). Bge(4) and ofw_pcibus(4) are
changed to use pci_find_dbsf(9) instead of pci_find_bsf(9) in order
to no longer report false positives when searching for siblings and
dupe devices in the same domain respectively.
Along with this change the sole host-PCI bridge driver converted to
actually make use of PCI domain support is uninorth(4), the others
continue to use domain 0 only for now and need to be converted as
appropriate later on.
Note that this means that the format of the location strings as used
by pciconf(8) has been changed and that consumers of <sys/pciio.h>
potentially need to be recompiled.

Suggested by:	jhb
Reviewed by:	grehan, jhb, marcel
Approved by:	re (kensmith), jhb (PCI maintainer hat)
2007-09-30 11:05:18 +00:00
Marius Strobl
ae3b789193 - Use the actual clock frequency of the PCI bus instead of assuming
33MHz for calculating the latency timer values for its children.
  Inspired by NetBSD doing the same and Linux as well as OpenSolaris
  using a similar approach.
  While at it rename a variable and change its type to be more
  appropriate fuer values of PCI properties so the variable can be
  more easily reused.
- Initialize the cache line size register of PCI devices to a
  legal value; the cache line size is limited to 64 bytes by the
  Fireplane/Safari, JBus and UPA interconnection busses. Setting
  it to an unsupported value caused bad performance at least with
  GEM as it causes them to not do cache line bursts and to not
  issue cache line commands on the PCI bus.

Approved by:	re (kensmith)
MFC after:	1 week
2007-09-26 20:10:36 +00:00
Marius Strobl
7439368f60 o Revamp the sparc64 interrupt code in order to be able to interface
with the INTR_FILTER-enabled MI code. Basically this consists of
  registering an interrupt controller (of which there can be multiple
  and optionally different ones either per host-to-foo bridge or shared
  amongst host-to-foo bridges in any one machine) along with an interrupt
  vector as specific argument for all the interrupt vectors used by a
  given host-to-foo bridge (roughly similar to registering interrupt
  sources on amd64 and i386), providing functions to enable, clear and
  disable the interrupts of the children beneath the bridge.
  This also includes:
  - No longer entering a critical section in tl0_intr() and tl1_intr()
    for executing interrupt handlers but rather let the handlers enter
    it themselves so in the case of intr_event_handle() we don't enter
    a nested critical section.
  - Adding infrastructure for binding delivery of interrupt vectors to
    specific CPUs which later on can be interfaced with the code from
    amd64/i386 for binding interrupts to specific CPUs.
  - Getting rid of the wrapper hack introduced along the lines of the
    API changes for INTR_FILTER which as a side-effect caused interrupts
    associated with ithread handlers only to get the elevated priority
    of those associated with filters ("fast handlers") (this removes the
    hack also in the non-INTR_FILTER case).
  - Disabling (by not clearing) an interrupt in the interrupt controller
    until all associated handlers have been executed, which is crucial
    for the typical locking strategy of NIC drivers in order to work
    correctly in case of shared interrupts. This was a more or less
    theoretical problem on sparc64 though, as shared interrupts are
    rather uncommon there except for the on-board SCCs and UARTs.
  Note that due to the behavior of at least of some of the interrupt
  controllers used on sparc64 an enable+EOI instead of a disable+EOI
  approach (as implied by the INTR_FILTER MI code and implemented on
  other architectures) is used as the latter can cause lost interrupts
  or in the worst case interrupt starvation.
o Correct a typo in sbus_alloc_resource() which caused (pass-through)
  allocations to only work down to the grandchildren of the bus, which
  wasn't a real problem so far as we don't support any devices which are
  great-grandchildren or greater of a U2S bridge, yet.
o In fhc(4) use bus_{read,write}_4() instead of bus_space_{read,write}_4()
  in order to get rid of sc_bh and sc_bt in the fhc_softc. Also get rid
  of some other unneeded members in fhc_softc.

Reviewed by:	marcel (earlier version)
Approved by:	re (kensmith)
2007-09-06 19:16:30 +00:00
Marius Strobl
6bbb5a106c - Divorce the IOTSBs, which so far where handled via a global list
instead of per IOMMU, so we no longer need to program all of them
  identically in systems having multiple IOMMUs. This continues the
  rototilling of the nexus(4) done about 5 months ago, which amongst
  others changed nexus(4) and the drivers for host-to-foo bridges
  to provide bus_get_dma_tag methods, allowing to handle DMA tags in
  a hierarchical way and to link them with devices.
  This still doesn't move the silicon bug workarounds for Sabre (and
  in the uncommitted schizo(4) for Tomatillo) bridges into special
  bus_dma_tag_create() and bus_dmamap_sync() methods though, as w/o
  fully newbus'ified bus_dma_tag_create() and bus_dma_tag_destroy()
  this still requires too much hackery, i.e. per-child parent DMA
  tags in the parent driver.
- Let the host-to-foo drivers supply the maximum physical address
  of the IOMMU accompanying the bridges. Previously iommu(4) hard-
  coded an upper limit of 16GB, which actually only applies to the
  IOMMUs of the Hummingbird and Sabre bridges. The Psycho variants
  as well as the U2S in fact can can translate to up to 2TB, i.e.
  translate to 41-bit physical addresses. According to the recently
  available Tomatillo documentation these bridges even translate to
  43-bit physical addresses and hints at the Schizo bridges doing
  43 bits as well.
  This fixes the issue the FreeBSD 6.0 todo list item "Max RAM on
  sparc64" was refering to and pretty much obsoletes the lack of
  support for bounce buffers on sparc64.

Thanks to Nathan Whitehorn for pointing me at the Tomatillo manual.

Approved by:	re (kensmith)
2007-08-05 11:56:44 +00:00