Commit Graph

29 Commits

Author SHA1 Message Date
Rebecca Cran
c90f7d9b44 Revert r216134. This checkin broke platforms where bus_space are macros:
they need to be a single statement, and do { } while (0) doesn't work in this
situation so revert until a solution can be devised.
2010-12-03 07:09:23 +00:00
Rebecca Cran
15b4888a24 Disallow passing in a count of zero bytes to the bus_space(9) functions.
Passing a count of zero on i386 and amd64 for [I386|AMD64]_BUS_SPACE_MEM
causes a crash/hang since the 'loop' instruction decrements the counter
before checking if it's zero.

PR:	kern/80980
Discussed with:	jhb
2010-12-02 22:19:30 +00:00
Warner Losh
01b5c01cae Remove clauses 3 and 4, per changes to NetBSD versions of these files. 2010-09-25 04:41:42 +00:00
Marcel Moolenaar
26279767e4 Some code churn:
o   Eliminate IA64_PHYS_TO_RR6 and change all places where the macro is used
    by calling either bus_space_map() or pmap_mapdev().
o   Implement bus_space_map() in terms of pmap_mapdev() and implement
    bus_space_unmap() in terms of pmap_unmapdev().
o   Have ia64_pib hold the uncached virtual address of the processor interrupt
    block throughout the kernel's life and access the elements of the PIB
    through this structure pointer.

This is a non-functional change with the exception of using ia64_ld1() and
ia64_st8() to write to the PIB. We were still using assignments, for which
the compiler generates semaphore reads -- which cause undefined behaviour
for uncacheable memory. Note also that the memory barriers in ipi_send() are
critical for proper functioning.

With all the mapping of uncached memory done by pmap_mapdev(), we can keep
track of the translations and wire them in the CPU. This then eliminates
the need to reserve a whole region for uncached I/O and it eliminates
translation traps for device I/O accesses.
2010-02-14 16:56:24 +00:00
Marcel Moolenaar
f7afeafebb Change BUS_SPACE_MAXADDR from 2^32-1 to 2^64-1. 2^32-1 is representative
for its origin, more than for its accuracy.

MFC after:	1 week
2010-01-02 00:37:00 +00:00
Marcel Moolenaar
938026e334 Revamp bus_space access functions:
o   Optimize for memory mapped I/O by making all I/O port acceses function
    calls and marking the test for the IA64_BUS_SPACE_IO tag with
    __predict_false(). Implement the I/O port access functions in a new
    file, called bus_machdep.c.
o   Change the bus_space_handle_t for memory mapped I/O to the virtual
    address rather than the physical address. This eliminates the PA->VA
    translation for every I/O access. The handle for I/O port access is
    still the port number.
o   Move inb(), outb(), inw(), outw(), inl(), outl(), and their string
    variants from cpufunc.h and define them in bus.h. On ia64 these are
    not CPU functions at all. In bus.h they are merely aliases for the
    new I/O port access functions defined in bus_machdep.h.
o   Handle the ACPI resource bug in nexus_set_resource(). There we can
    do it once so that we don't have to worry about it whenever we need
    to write to an I/O port that is really a memory mapped address.

The upshot of this change is that the KBI is better defined and that I/O
port access always involves a function call, allowing us to change the
actual implementation without breaking the KBI. For memory mapped I/O the
virtual address is abstracted, so that we can change the VA->PA mapping
in the kernel without causing an KBI breakage. The exception at this time
is for bus_space_map() and bus_space_unmap().

MFC after:	1 week.
2009-12-30 18:15:25 +00:00
Marcel Moolenaar
4827e0cd5c Make sure bus space accesses use unorder memory loads and stores.
Memory accesses are posted in program order by virtue of the
uncacheable memory attribute.
Since GCC, by default, adds acquire and release semantics to
volatile memory loads and stores, we need to use inline assembly
to guarantee it. With inline assembly, we don't need volatile
pointers anymore.

Itanium does not support semaphore instructions to uncacheable
memory.
2009-12-03 04:06:48 +00:00
Yoshihiro Takahashi
d4fcf3cba5 Remove bus_{mem,p}io.h and related code for a micro-optimization on i386
and amd64.  The optimization is a trivial on recent machines.

Reviewed by:	-arch (imp, marcel, dfr)
2005-05-29 04:42:30 +00:00
Marcel Moolenaar
6fab4fece2 Don't define _MACHINE_BUS_MEMIO_H_ nor _MACHINE_BUS_PIO_H_. 2005-05-10 02:59:24 +00:00
Warner Losh
06db52b609 Break out the definition of bus_space_{tag,handle}_t and a few other types
into _bus.h to help with name space polution from including all of bus.h.
In a few days, I'll commit changes to the MI code to take advantage of thse
sepration (after I've made sure that these changes don't break anything in
the main tree, I've tested in my trees, but you never know...).

Suggested by: bde (in 2002 or 2003 I think)
Reviewed in principle by: jhb
2005-04-18 21:45:34 +00:00
Scott Long
5974e5c71c Refactor the bus_dma header files so that the interface is described in
sys/bus_dma.h instead of being copied in every single arch.  This slightly
reorders a flag that was specific to AXP and thus changes the ABI there.
The interface still relies on bus_space definitions found in <machine/bus.h>
so it cannot be included on its own yet, but that will be fixed at a later
date.  Add an MD <machine/bus_dma.h> for ever arch for consistency and to
allow for future MD augmentation of the API.  sparc64 makes heavy use of
this right now due to its different bus_dma implemenation.
2005-03-14 16:46:28 +00:00
Scott Long
33072f4de7 Add bus_dmamap_load_mbuf_sg() to ia64 2005-01-15 19:26:17 +00:00
Warner Losh
86cb007f9f /* -> /*- for copyright notices, minor format tweaks as necessary 2005-01-06 22:18:23 +00:00
Scott Long
eb3b7bf69f Document the lockfunc and lockfuncarg arguments to bus_dma_tag_create() in
the busdma headers.
2003-11-07 23:29:42 +00:00
Yoshihiro Takahashi
33e38a2cc8 Implement the bus_space_map() function to allocate resources and initialize
a bus_handle, but currently it does only initializing a bus_handle.
2003-09-23 08:22:34 +00:00
Maxime Henrion
d5afecd068 - Introduce a new busdma flag BUS_DMA_ZERO to request for zero'ed
memory in bus_dmamem_alloc().  This is possible now that
  contigmalloc() supports the M_ZERO flag.
- Remove the locking of Giant around calls to contigmalloc() since
  contigmalloc() now grabs Giant itself.
2003-07-27 13:52:10 +00:00
Scott Long
f6b1c44d1f Mega busdma API commit.
Add two new arguments to bus_dma_tag_create(): lockfunc and lockfuncarg.
Lockfunc allows a driver to provide a function for managing its locking
semantics while using busdma.  At the moment, this is used for the
asynchronous busdma_swi and callback mechanism.  Two lockfunc implementations
are provided: busdma_lock_mutex() performs standard mutex operations on the
mutex that is specified from lockfuncarg.  dftl_lock() is a panic
implementation and is defaulted to when NULL, NULL are passed to
bus_dma_tag_create().  The only time that NULL, NULL should ever be used is
when the driver ensures that bus_dmamap_load() will not be deferred.
Drivers that do not provide their own locking can pass
busdma_lock_mutex,&Giant args in order to preserve the former behaviour.

sparc64 and powerpc do not provide real busdma_swi functions, so this is
largely a noop on those platforms.  The busdma_swi on is64 is not properly
locked yet, so warnings will be emitted on this platform when busdma
callback deferrals happen.

If anyone gets panics or warnings from dflt_lock() being called, please
let me know right away.

Reviewed by:	tmm, gibbs
2003-07-01 15:52:06 +00:00
Hiten Pandya
b77c32a07e Rename BUS_DMAMEM_NOSYNC to BUS_DMA_COHERENT.
The current name is confusing, because it indicates to
the client that a bus_dmamap_sync() operation is not
necessary when the flag is specified, which is wrong.

The main purpose of this flag is to hint the underlying
architecture that DMA memory should be mapped in a coherent
way, but the architecture can ignore it.  But if the
architecture does supports coherent mapping of memory, then
it makes bus_dmamap_sync() calls cheap.

This flag is the same as the one in NetBSD's Bus DMA.

Reviewed by: gibbs, scottl, des (implicitly)
Approved by: re@ (jhb)
2003-05-30 20:40:33 +00:00
Scott Long
7e71df9339 Bring back bus_dmasync_op_t. It is now a typedef to an int, though the
BUS_DMASYNC_ definitions remain as before.  The does not change the ABI,
and reverts the API to be a bit more compatible and flexible.  This has
survived a full 'make universe'.

Approved by:	re (bmah)
2003-05-27 04:59:59 +00:00
Marcel Moolenaar
c283dd9dad Revamp the newbus functions:
o  do not use the in* and out* functions. These functions are used by
   legacy drivers and thus must have ia32 compatible behaviour. Hence,
   they  need to have fences. Using these functions for newbus would
   then pessimize performance.
o  remove the conditional compilation of PIO and/or MEMIO support. It's
   a PITA without having any significant benefit. We always support them
   both. Since there are no I/O ports on ia64 (they are simulated by the
   chipset by translating memory mapped I/O to predefined uncacheable
   memory regions) the only difference between PIO and MEMIO is in the
   address calculation. There should be enough ILP that can be exploited
   here that making these computations compile-time conditional is not
   worth it. We now also don't use the read* and write* functions.
o  Add the missing *_8 variants. They were missing, although not missed.
   It's for completeness.
o  Do not add the fences that were present in the low-level support
   functions here. We're using uncacheable memory, which means that
   accesses are in program order. Change the barrier implementation
   to not only do a memory fence, but also an acceptance fence. This
   should more reliably synchronize drivers with the hardware. The
   memory fence enforces ordering, but does not imply visibility (ie
   the access does not necessarily have happened). This is what the
   acceptance deals with.

cpufunc.h cleanup:
o  Remove the low-level memory mapped I/O support functions. They are
   not used. Keep the low-level I/O port access functions for legacy
   drivers and add fences to ensure ia32 compatibility.
o  Remove the syscons specific functions now that we have moved the
   proper definitions where they belong.
o  Replace the ia64_port_address() and ia64_memory_address() functions
   with macros. There's a bigger change inline functions get inlined
   when there aren't function callsi and the calculations are simply
   enough to do it with macros.

Replace the one reference to ia64_memory address in mp_machdep.c to
use the macro.
2003-04-29 09:50:03 +00:00
Maxime Henrion
7a648f56cf I deserve a big pointy hat for having missed all those references
to bus_dmasync_op_t in my last commit.
2003-04-10 23:50:06 +00:00
Maxime Henrion
f6c912dd0c Correctly set BUS_SPACE_MAXSIZE in all the busdma backends.
It was bogusly set to 64 * 1024 or 128 * 1024 because it was
bogusly reused in the BUS_DMAMAP_NSEGS definition.
2003-02-26 02:16:06 +00:00
Marcel Moolenaar
aa063fddbf Provide a null-implementation for bus_space_unmap, like i386.
bus_space_unmap is required for puc(4).
2003-01-05 21:34:05 +00:00
Marcel Moolenaar
4ea25f94be Implement bus_space_subregion(). Identical to i386.
Approved by: re (carte blanc)
2002-11-29 20:14:03 +00:00
Sam Leffler
14c17bd293 New bus_dma interfaces for use by crypto device drivers:
o bus_dmamap_load_mbuf
o bus_dmamap_load_uio

Test on i386.  Known to compile on alpha and sparc64, but not tested.
Otherwise untried.
2002-10-04 20:40:39 +00:00
Thomas Moestl
90ce56c287 Add the following functions/macros to support byte order conversions and
device drivers for bus system with other endinesses than the CPU (using
interfaces compatible to NetBSD):

- bwap16() and bswap32(). These have optimized implementations on some
  architectures; for those that don't, there exist generic implementations.
- macros to convert from a certain byte order to host byte order and vice
  versa, using a naming scheme like le16toh(), htole16().
  These are implemented using the bswap functions.
- stream bus space access functions, which do not perform a byte order
  conversion (while the normal access functions would if the bus endianess
  differs from the CPU endianess).

htons(), htonl(), ntohs() and ntohl() are implemented using the new
functions above for kernel usage. None of the above interfaces is currently
exported to user land.

Make use of the new functions in a few places where local implementations
of the same functionality existed.

Reviewed by:	mike, bde
Tested on alpha by:	mike
2002-02-27 17:16:18 +00:00
John Baldwin
3f4809dd0d Axe the barrier_{read,write,rw}() helper functions as this method of
doing memory barriers doesn't really scale well for the ia64.  Also,
memory barriers are more a property of the CPU than bus space.

Requested by:	dfr
2000-10-20 06:45:48 +00:00
John Baldwin
25f3f7c530 Add in a simple API for memory barriers to machine/bus.h:
- barrier_read() enforces a memory read barrier
- barrier_write() enforces a memory write barrier
- barrier_rw() enforces a memory read/write barrier
2000-10-18 10:30:12 +00:00
Doug Rabson
1ebcad5720 This is the first snapshot of the FreeBSD/ia64 kernel. This kernel will
not work on any real hardware (or fully work on any simulator). Much more
needs to happen before this is actually functional but its nice to see
the FreeBSD copyright message appear in the ia64 simulator.
2000-09-29 13:46:07 +00:00