means:
o Remove Elf64_Quarter,
o Redefine Elf64_Half to be 16-bit,
o Redefine Elf64_Word to be 32-bit,
o Add Elf64_Xword and Elf64_Sxword for 64-bit entities,
o Use Elf_Size in MI code to abstract the difference between
Elf32_Word and Elf64_Word.
o Add Elf_Ssize as the signed counterpart of Elf_Size.
MFC after: 2 weeks
o Remove the unused and non-standard SHT_NUM, PT_COUNT and DT_COUNT.
o Add the STV_DEFAULT, STV_INTERNAL, STV_HIDDEN and STV_PROTECTED
symbol visibility constants.
o Add the ELF32_ST_VISIBILITY and ELF64_ST_VISIBILITY macros to
get the symbol visibility from the st_other field.
o Add the ELFOSABI_AIX, ELFOSABI_OPENVMS and ELFOSABI_NSK constants.
o Add the ET_LOOS, ET_HIOS, ET_LOPROC and ET_HIPROC constants.
o Further flesh out the list of machine types. Note that EM_ALPHA
remains non-standard. The standard value for EM_ALPHA is given
by EM_ALPHA_STD (which is a non-standard name :-)
o Add the SHN_LOOS, SHN_HIOS and SHN_XINDEX constants.
o Add the SHT_INIT_ARRAY, SHT_FINI_ARRAY, SHT_PREINIT_ARRAY, SHT_GROUP
and SHT_SYMTAB_SHNDX constants.
o Add the SHF_MERGE, SHF_STRINGS, SHF_INFO_LINK, SHF_LINK_ORDER,
SHF_OS_NONCONFORMING, SHF_GROUP and SHF_MASKOS constants.
o Add the PF_MASKOS and PF_MASKPROC constants.
o Add the STB_LOOS andf STB_HIOS constants.
o Add the STT_COMMON, STT_LOOS and STT_HIOS constants.
MFC after: 1 week
32-bit entity. Also, don't cast the resulting symbol type value to
a datatype smaller than the st_info field type as a quick way to
mask off the upper bits as it may cause inconsistent behaviour when
the macro is used (without explicit casting) on varargs functions.
MFC after: 1 week
span ports when they disappear. The span port does not have a pointer to the
softc so revert r1.31 and bring back the softc linked-list.
MFC after: 2 weeks
and KTR_IO as they were never used. Remove KTR_CLK since it was only
used for hardclock firing and use KTR_INTR there instead. Remove
KTR_CRITICAL since it was only used for crit enter/exit and use
KTR_CONTENTION instead.
AMD-8111 SMBus 2.0 controller) are all SMBus 2.0 controllers,
and need another implementation of SMBus access methods, while
this driver supports AMD-756 SMBus 1.0 controller and clones,
including AMD-8111 SMBus 1.0 controller.
Tested by: Vladimir Timofeev (0x006410de),
mezz (0x008410de),
ru (0x00d410de)
All of us got the same(!) nonsense when running ``mbmon -S'',
repeated every four rows.
really should be a fptrdiff_t if we had that) in profclock().
- Don't try to profile kernel pc's that are >= the kernel lowpc to avoid
underflows when computing a profiling index.
- Use the PC_TO_I() macro to compute the kernel profiling index rather than
doing it inline.
Discussed with: bde
ephemeral mappings that are used as the source for three copy
operations from kernel space to user space. There are two reasons for
making this change: (1) Under heavy load exec_map can fill up causing
vm_map_find() to fail. When it fails, the nascent process is aborted
(SIGABRT). Whereas, this reimplementation using sf_buf_alloc()
sleeps. (2) Although it is possible to sleep on vm_map_find()'s
failure until address space becomes available (see kmem_alloc_wait()),
using sf_buf_alloc() is faster. Furthermore, the reimplementation
uses a CPU private mapping, avoiding a TLB shootdown on
multiprocessors.
Problem uncovered by: kris@
Reviewed by: tegge@
MFC after: 3 weeks
SMBus 1.0 and not SMBus 2.0.
AMD-8111 hub (datasheet is publically available) implements both SMBus
2.0 (a separate PCI device) and SMBus 1.0 (a subfunction of the System
Management Controller device with the base I/O address is accessible
through the CSR 0x58). This driver only supports AMD-756 SMBus 1.0
compatible devices.
With the patched sysutils/xmbmon port (to also fix PCI ID and to enable
smb(4) support), I now get:
pciconf:
none0@pci0:7:2: class=0x0c0500 card=0x746a1022 chip=0x746a1022 rev=0x02 hdr=0x00
vendor = 'Advanced Micro Devices (AMD)'
device = 'AMD-8111 SMBus 2.0 Controller'
class = serial bus
subclass = SMBus
amdpm0@pci0:7:3: class=0x068000 card=0x746b1022 chip=0x746b1022 rev=0x05 hdr=0x00
vendor = 'Advanced Micro Devices (AMD)'
device = 'AMD-8111 ACPI System Management Controller'
class = bridge
dmesg:
amdpm0: <AMD 756/766/768/8111 Power Management Controller> port 0x10e0-0x10ff at device 7.3 on pci0
smbus0: <System Management Bus> on amdpm0
# mbmon -A -d
Summary of Detection:
* SMB monitor(s)[ioctl:AMD8111]:
** Winbond Chip W83627HF/THF/THF-A found at slave address: 0x50.
** Analog Dev. Chip ADM1027 found at slave address: 0x5C.
* ISA monitor(s):
** Winbond Chip W83627HF/THF/THF-A found.
I think the confusion comes from the fact that nobody really tried
SMBus with xmbmon :-), since sysutils/xmbmon port doesn't come with
SMBus support enabled, neither in FreeBSD 4, nor in later versions,
so mbmon(1) was just showing the values from the Winbond sensors
accessible through the ISA I/O method (mbmon -I), for me anyway.
On my test machine, the amdpm(4) didn't even attach due to I/O port
allocation failure (who knows what the hell it read from CSR 0x58
of the SMBus 2.0 device :-), which isn't in the CSR space).
I've also checked that lm_sensors.org uses correct PCI ID for SMBus
1.0 of AMD-8111:
i2c-amd756.c: {PCI_VENDOR_ID_AMD, 0x746B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, AMD8111 },
This driver is analogous to our amdpm.c which supports SMBus 1.0
AMD-756 and compatible devices, including SMBus 1.0 on AMD-8111.
i2c-amd8111.c: { 0x1022, 0x746a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
This driver is analogous to nForce-2/3/4, i2c-nforce2.c, which
supports SMBus 2.0, and which our amdpm.c does NOT support
(SMBus 2.0 uses a different, ACPI-unified, API to talk to SMBus).
At least I know for sure it doesn't work with my nForce3. :-)
(The xmbmon port will be fixed to correct the PCI ID too and to
enable the smb(4) support.)
command. This fixes some weird booting issues on newer versions
of the firmware on the MSA20.
Reported by: Philippe Pegon <Philippe dot Pegon at crc dot u-strasbg dot fr>
which existed to cleanup the linux_osname mutex. Now that MTX_SYSINIT()
has grown a SYSUNINIT to destroy mutexes on unload, the extra destroy here
was redundant and resulted in panics in debug kernels.
MFC after: 1 week
Reported by: Goran Gajic ggajic at afrodita dot rcub dot bg dot ac dot yu
- Give up endianess support and switch to native-endian format for
accessing hardware structures. In fact embedded processor for
BCM57xx is big-endian architure(MIPS) and it requires native-endian
format for NIC structures.The NIC performs necessary byte/word
swapping depending on programmed endian type.
- With above changes all htole16/htole32 calls were gone.
- Remove bge_vhandle member in softc and changed to use explicit
register access. This may add additional performance penalty
that than that of previous memory access. But most of the access
is performed on initialization phase(e.g. RCB setup), it would be
negligible.
Due to incorrect use of bus_dma(9) in bge(4) it still panics sparc64
system in device detach path. The issue would be fixed in next patch.
Reviewed by: jkim (initial version)
Silence from: ps
Tested by: glebius
Obtained from: NetBSD via OpenBSD
mbuf chain that starts with a cluster containing just MHLEN bytes. This
happened because m_dup called m_get or m_getcl depending on the amount of
data to copy, but then always set the size available in the first mbuf to
MHLEN.
Submitted by: Matt Koivisto <mkoivisto at sandvine dot com>
Approved by: jmg
Silence from: rwatson (mentor)
SMBus busses. Because of limitations in smbus_if.m, the second smbus is
attached to an amdpm1 device that is a child of amdpm0.
Submitted by: Artemiev Igor ai (at) bmc dot brk dot ru
1. Implement a large set of ioctl shims so that the Linux management apps
from LSI will work. This includes infrastructure to support adding, deleting
and rescanning arrays at runtime. This is based on work from Doug Ambrosko,
heavily augmented by LSI and Yahoo.
2. Implement full 64-bit DMA support. Systems with more than 4GB of RAM
can now operate without the cost of bounce buffers. Cards that cannot do
64-bit DMA will automatically revert to using bounce buffers. This option
can be forced off by setting the 'hw.amr.force_sg32" tunable in the loader.
It should only be turned off for debugging purposes. This work was sponsored
by Yahoo.
3. Streamline the command delivery and interrupt handler paths after
much discussion with Dell and LSI. The logic now closely matches the
intended design, making it both more robust and much faster. Certain
i/o failures under heavy load should be fixed with this.
4. Optimize the locking. In the interrupt handler, the card can be checked
for completed commands without any locks held, due to the handler being
implicitely serialized and there being no need to look at any shared data.
Only grab the lock to return the command structure to the free pool. A
small optimization can still be made to collect all of the completions
together and then free them together under a single lock.
Items 3 and 4 significantly increase the performance of the driver. On an
LSI 320-2X card, transactions per second went from 13,000 to 31,000 in my
testing with these changes. However, these changes are still fairly
experimental and shouldn't be merged to 6.x until there is more testing.
Thanks to Doug Ambrosko, LSI, Dell, and Yahoo for contributing towards
this.
