- catch the interrupt type (EDGE/LEVEL) before chip reset instead
of guessing the right type.
- Add pause variable to the ahc struct to better handle the different
interrupt types and pausing the sequencer.
- CLRINTSTAT -> CLRSCSIINT: This is a documented bit in the CLRINT
register in newer Adaptec documentation, so use their name for it.
- Report valid residual byte counts.
- Don't mess with the target scratch areas > id 8 on single, narrow,
channel devices. The BIOS does a checksum of this area and can
flip out if we zero it out.
- Initialize the sequencer FLAGS scratch ram variable in the single
channel devices to 0. This was the cause of the annoying warning
where we would get a cmdcmplt the first time we did any type of
transfer negotiation with no valid scb. It also fixes the problem
that looked like the INTSTAT register wasn't clearing fast enough.
This only showed up on 294x cards, not motherboard aic7870s.
- Add the AHC_AIC7870 type and use it as the superset of aic7870
based controllers.
- clear the sync offset section of the targ scratch area so that
we default to asyncronous transfers. This was only a problem
for wide controllers because there was a scenario where the
offset wouldn't get updated before a data(out/in) phase would
occur. This required some change in the sequencer code since we
were depending on this field to hold the rate to negotiate.
- allow sync and wide negotiated commands to be tagged (the sequencer
now handles this properly).
commands per target. I could have followed the route of the ncr driver
and gone to great lengths to get the SCSI subsystem to support more, but
I think I'll use the time saved to help Julian and Peter make tagged
queuing a better handled generic feature. This also includes some comment
and enum clean up and a possible fix for the hanging PCI controllers.
message instead of relying on the fact that we are scheduled to send them.
The old method worked 99.9% of the time, but someone reported some periferals
that did MSG_REJECT at odd times (sometimes before we could send an SDTR
or WDTR) that we would construe as the response to an SDTR or WDTR message.
This also removes a possible race condition where after a bus reset (the
result of a command time out not during intial probe time), we might queue
two commands both requesting SDTR, WDTR or both.
WDTR, and message reject handlers so they don't need to exist in the
sequencer. All three of these cases are not on the critical path, so it
makes little sense to use up precious sequencer ram for them.
