Commit Graph

3355 Commits

Author SHA1 Message Date
Maxim Sobolev
df86dcaf67 Fix typo in comments in r189023. 2009-02-25 22:24:56 +00:00
Jung-uk Kim
a4079bfb74 Enable support for PAT_WRITE_PROTECTED and PAT_UNCACHED cache modes
unconditionally on amd64.  On i386, we assume PAT is usable if the CPU
vendor is not Intel or CPU model is newer than Pentium IV.

Reviewed by:	alc, jhb
2009-02-25 20:26:48 +00:00
Maxim Sobolev
e0bc0fad3d Make machdep.hyperthreading_enabled tunable working with the SCHED_ULE.
Unlike with SCHED_BSD, however, it can only be set to 0 at boot time,
it's not possible to change it at runtime.

Reviewed by:	jhb
MFC after:	1 month
2009-02-25 01:49:01 +00:00
John Baldwin
0b7dc0a7c6 Some whitespace and style fixes.
Submitted by:	bde (partly)
2009-02-23 15:39:24 +00:00
Alan Cox
6d65f2fa57 Optimize free_pv_entry(); specifically, avoid repeated TAILQ_REMOVE()s.
MFC after:	1 week
2009-02-23 06:00:24 +00:00
Jeff Roberson
35d8de82c4 - Resolve an issue where we may clear an idt while an interrupt on a
different cpu is still assigned to that vector by never clearing idt
   entries.  This was only provided as a debugging feature and the bugs
   are caught by other means.
 - Drop the sched lock when rebinding to reassign an interrupt vector
   to a new cpu so that pending interrupts have a chance to be delivered
   before removing the old vector.

Discussed with:	tegge, jhb
2009-02-21 23:15:34 +00:00
Alan Cox
6be00eca3f Remove unnecessary page queues locking around vm_page_busy() and
vm_page_wakeup().  (This change is applicable to RELENG_7 but not
RELENG_6.)

MFC after:	1 week
2009-02-14 18:23:52 +00:00
Olivier Houchard
96c7367b9e The bounce zone sees its page number increased if multiple dma maps use it in
the same dma tag. However, it can happen multiple dma tags share the same
bounce zone too, so add a per-bounce zone map counter, and check it instead of
the dma tag map counter, to know if we have to alloc more pages.

Reported by:	miwi
Reviewed by:	scottl
2009-02-09 18:03:31 +00:00
Warner Losh
047e5fdabc When bouncing pages, allow a new option to preserve the intra-page
offset.  This is needed for the ehci hardware buffer rings that assume
this behavior.

This is an interim solution, and a more general one is being worked
on.  This solution doesn't break anything that doesn't ask for it
directly.  The mbuf and uio variants with this flag likely don't work
and haven't been tested.

Universe builds with these changes.  I don't have a huge-memory
machine to test these changes with, but will be happy to work with
folks that do and hps if this changes turns out not to be sufficient.

Submitted by:	alfred@ from Hans Peter Selasky's original
2009-02-08 22:54:58 +00:00
Joseph Koshy
bb471e3315 Improve robustness of NMI handling, for NMIs recognized in kernel
mode.

- Make the NMI handler run on its own stack (TSS_IST2).
- Store the GSBASE value for each CPU just before the start of
  each NMI stack, permitting efficient retrieval using %rsp-relative
  addressing.
- For NMIs taken from kernel mode, program MSR_GSBASE explicitly
  since one or both of MSR_GSBASE and MSR_KGSBASE can be potentially
  invalid.  The current contents of MSR_GSBASE are saved and restored
  at exit.
- For NMIs handled from user mode, continue to use 'swapgs' to
  load the per-CPU GSBASE.

Reviewed by:	jeff
Debugging help:	jeff
Tested by:	gnn, Artem Belevich <artemb at gmail dot com>
2009-02-03 09:01:45 +00:00
David E. O'Brien
e6493bbebf Change some movl's to mov's. Newer GAS no longer accept 'movl' instructions
for moving between a segment register and a 32-bit memory location.

Looked at by:	jhb
2009-01-31 11:37:21 +00:00
Jeff Roberson
9c8e8e3aa7 - Allocate apic vectors on a per-cpu basis. This allows us to allocate
more irqs as we have more cpus.  This is principally useful on systems
   with msi devices which may want many irqs per-cpu.

Discussed with:	jhb
Sponsored by:	Nokia
2009-01-29 09:22:56 +00:00
John Baldwin
de43ac6044 Use a different value for the initial control word for the FPU state for
32-bit processes.  The value matches the initial setting used by
FreeBSD/i386.  Otherwise, 32-bit binaries using floating point would use
a slightly different initial state when run on FreeBSD/amd64.

MFC after:	1 week
2009-01-28 20:35:16 +00:00
Jung-uk Kim
b11e7979ac VIA Nano processor has a special MSR (CENT_HARDWARECTRL3) bit 32 to determine
whether TSC is P-state invariant or not.  In fact, this MSR is writable but
we just leave it at the BIOS default for now.
2009-01-22 21:04:46 +00:00
Konstantin Belousov
5c0c22e92e The context switch to the 32bit binary does not properly restore
the fsbase value. The switch loads the fs segment register, that
invalidates the value in fsbase msr, thus value in %r9 can not be
considered the current value for fsbase anymore.

Unconditionally reload fsbase when switching to 32bit binary.

PR:	130526
MFC after:	3 weeks
2009-01-20 12:07:49 +00:00
Konstantin Belousov
a353a3455e Disable interrupts, if they were enabled, before doing swapgs.
Otherwise, interrupt may happen while we run with kernel CS and usermode
gsbase.

Reviewed by:	jeff
MFC after:	1 week
2009-01-14 14:20:08 +00:00
Jung-uk Kim
92df0bda99 Add basic amd64 support for VIA Nano processors. 2009-01-12 19:17:35 +00:00
Jung-uk Kim
6811e5d474 Add Centaur/IDT/VIA vendor ID for Nano family, which has long mode support. 2009-01-05 21:51:49 +00:00
Joseph Koshy
4e706fe392 Bug fix: %ebx needs to be preserved in the user callchain capture
path.
2008-12-14 09:06:28 +00:00
Joseph Koshy
6fe00c7876 - Bug fix: prevent a thread from migrating between CPUs between the
time it is marked for user space callchain capture in the NMI
  handler and the time the callchain capture callback runs.

- Improve code and control flow clarity by invoking hwpmc(4)'s user
  space callchain capture callback directly from low-level code.

Reviewed by:	jhb (kern/subr_trap.c)
Testing (various patch revisions): gnn,
		Fabien Thomas <fabien dot thomas at netasq dot com>,
		Artem Belevich <artemb at gmail dot com>
2008-12-13 13:07:12 +00:00
Jung-uk Kim
39e52304e0 Add more CPUID bits from AMD CPUID Specification Rev. 2.28. 2008-12-12 23:17:00 +00:00
Joseph Koshy
5abe7b5623 Expose symbol `PMC_FN_USER_CALLCHAIN' to assembler code. 2008-12-12 16:09:34 +00:00
John Baldwin
660f08b291 Add constants for fields in the local APIC error status register and a
routine to read it.
2008-12-11 15:56:30 +00:00
Alan Cox
e0d315046b Change the default value for the flag enabling superpage mapping and
promotion to "on".

Reminded by:	jhb
Tested by:	kris
2008-12-06 19:37:52 +00:00
Konstantin Belousov
482b7172da Improve db_backtrace() for compat ia32 on amd64. 32bit image enters
the kernel via Xint0x80_syscall().

Submitted by:	dchagin
MFC after:	1 week
2008-12-05 11:34:36 +00:00
Ganbold Tsagaankhuu
7613f162e9 Remove unused variable.
Found with:     Coverity Prevent(tm)
CID: 3685

Approved by: jhb
2008-12-02 14:19:53 +00:00
Alexander Motin
9ee5eabc3f According to "Intel 64 and IA-32 Architectures Software Developer's Manual
Volume 3B: System Programming Guide, Part 2", CPUs with family 0x6 and model
above or 0xE and CPUs with family 0xF and model above or 0x3 have invariant
TSC.
2008-11-30 00:10:55 +00:00
Jung-uk Kim
0eec8b9141 Use newly introduced cpu_vendor_id to make invariant TSC detection more
clearer and merge r185295 to amd64.
2008-11-26 19:29:33 +00:00
Jung-uk Kim
5113aa0af3 Introduce cpu_vendor_id and replace a lot of strcmp(cpu_vendor, "...").
Reviewed by:	jhb, peter (early amd64 version)
2008-11-26 19:25:13 +00:00
Konstantin Belousov
b4cf0e62f4 Add sv_flags field to struct sysentvec with intention to provide description
of the ABI of the currently executing image. Change some places to test
the flags instead of explicit comparing with address of known sysentvec
structures to determine ABI features.

Discussed with:	dchagin, imp, jhb, peter
2008-11-22 12:36:15 +00:00
Konstantin Belousov
f5dfdb519f Revert r184136. Instead, push the check for crashdumpmap overflow into the
MD i386 and amd64 dump code.

Requested by:	jhb
Retested by:	pho
MFC after:	3 days (+ 176304 + 184136)
2008-10-31 10:11:35 +00:00
Maxim Sobolev
f06b09959d Fix r184323 - set stathz to be the same as lapic_timer_hz when lapic_timer_hz
is less than 128. Remove extra {} to match existing style.
2008-10-27 21:45:18 +00:00
Maxim Sobolev
b7865f7912 Fix division by zero panic if kern.hz less than 32.
MFC after:	1 day
2008-10-26 18:58:04 +00:00
Jung-uk Kim
0c0c75a824 Add AMD Family 0Fh, Model 6Bh, Stepping 2 to the list of invariant TSCs
and fix i386 test.
2008-10-22 17:30:37 +00:00
Jung-uk Kim
87c919e808 Set kern.timecounter.invariant_tsc to 1 for AMD CPU family 10h and higher
even if BIOS does not advertise it.
2008-10-22 00:01:53 +00:00
Jung-uk Kim
29462bea1e Turn off CPU frequency change notifiers when the TSC is P-state invariant
or it is forced by setting 'kern.timecounter.invariant_tsc' tunable
to non-zero.
2008-10-21 00:38:00 +00:00
Jung-uk Kim
780f139b5b Detect Advanced Power Management Information for AMD CPUs. 2008-10-21 00:17:55 +00:00
David Xu
7ce5e15ebe If the current thread has the trap bit set (i.e. a debugger had
single stepped the process to the system call), we need to clear
the trap flag from the new frame. Otherwise, the new thread will
receive a (likely unexpected) SIGTRAP when it executes the first
instruction after returning to userland.
2008-10-05 02:03:54 +00:00
Peter Wemm
e6592ee55c Collect N identical (or near identical) mkdumpheader() implementations into
one, as threatened in the comment.  Textdump magic can be passed in.
2008-10-01 22:08:53 +00:00
Marius Strobl
6f04e7b9aa Remove ipi_all() and ipi_self() as the former hasn't been used at
all to date and the latter also is only used in ia64 and powerpc
code which no longer serves a real purpose after bring-up and just
can be removed as well. Note that architectures like sun4u also
provide no means of implementing IPI'ing a CPU itself natively
in the first place.

Suggested by:	jhb
Reviewed by:	arch, grehan, jhb
2008-09-28 18:34:14 +00:00
Ed Schouten
6bfa9a2d66 Replace all calls to minor() with dev2unit().
After I removed all the unit2minor()/minor2unit() calls from the kernel
yesterday, I realised calling minor() everywhere is quite confusing.
Character devices now only have the ability to store a unit number, not
a minor number. Remove the confusion by using dev2unit() everywhere.

This commit could also be considered as a bug fix. A lot of drivers call
minor(), while they should actually be calling dev2unit(). In -CURRENT
this isn't a problem, but it turns out we never had any problem reports
related to that issue in the past. I suspect not many people connect
more than 256 pieces of the same hardware.

Reviewed by:	kib
2008-09-27 08:51:18 +00:00
Konstantin Belousov
a8d403e102 Change the static struct sysentvec and struct Elf_Brandinfo initializers
to the C99 style. At least, it is easier to read sysent definitions
that way, and search for the actual instances of sigcode etc.

Explicitely initialize sysentvec.sv_maxssiz that was missed in most
sysvecs.

No objection from:	jhb
MFC after:	1 month
2008-09-24 10:14:37 +00:00
Stanislav Sedov
4f55a298ce - Recognize SAVE and OSXSAVE extended processor features.
Approved by:	kib (mentor)
MFC after:	1 month
2008-09-18 18:51:32 +00:00
John Baldwin
289f40c67b Update the comments above the 0xcf9 register reset attempt to match the
code.  We only attempt a single reset using this method (a "hard" reset),
and we use two writes to ensure there is a 0 -> 1 transition in bit 2 to
force a reset.

MFC after:	1 week
2008-09-11 18:33:57 +00:00
Konstantin Belousov
3bd5e467b2 The pcb_gs32p should be per-cpu, not per-thread pointer. This is
location in GDT where the segment descriptor from pcb_gs32sd is
copied, and the location is in GDT local to CPU.

Noted and reviewed by:	peter
MFC after:	1 week
2008-09-08 09:59:05 +00:00
Konstantin Belousov
1772c3e9bb Provide private per-CPU GDTs on amd64. This is required at least for the
linux CB_GS32BIT to work.

Noted by:	nox
Reviewed by:	peter
MFC after:	1 week
2008-09-08 09:55:51 +00:00
Konstantin Belousov
575a30d883 Fix inconsistencies in the comments.
MFC after:	1 week
2008-09-08 08:58:29 +00:00
Konstantin Belousov
f98c3ea74e - When executing FreeBSD/amd64 binaries from FreeBSD/i386 or Linux/i386
processes, clear PCB_32BIT and PCB_GS32BIT bits [1].

- Reread the fs and gs bases from the msr unconditionally, not believing
  the values in pcb_fsbase and pcb_gsbase, since usermode may reload
  segment registers, invalidating the cache. [2].

Both problems resulted in the wrong fs base, causing wrong tls pointer
be dereferenced in the usermode.

Reported and tested by:	Vyacheslav Bocharov <adeepv at gmail com> [1]
Reported by:	Bernd Walter <ticsoat cicely7 cicely de>,
	Artem Belevich <fbsdlist at src cx>[2]
Reviewed by:	peter
MFC after:	3 days
2008-09-02 17:52:11 +00:00
Jung-uk Kim
a2b12e3b23 Move empty filter handling to MI source.
MFC after:	3 days
2008-08-26 21:06:31 +00:00
Jung-uk Kim
f471e5690e Fix a typo in copyrights. 2008-08-25 20:43:13 +00:00