Commit Graph

32 Commits

Author SHA1 Message Date
Ruslan Bukin
4d3b6bd5df Follow r317061 "Remove struct vmmeter from struct pcpu"
with MD changes for RISC-V.

This unbreaks RISC-V build.

Sponsored by:	DARPA, AFRL
2017-04-19 17:06:32 +00:00
Patrick Kelsey
67d955aab4 Corrected misspelled versions of rendezvous.
The MFC will include a compat definition of smp_no_rendevous_barrier()
that calls smp_no_rendezvous_barrier().

Reviewed by:	gnn, kib
MFC after:	1 week
Differential Revision:	https://reviews.freebsd.org/D10313
2017-04-09 02:00:03 +00:00
Bruce Evans
f434f3515b Fix printing of negative offsets (typically from frame pointers) again.
I fixed this in 1997, but the fix was over-engineered and fragile and
was broken in 2003 if not before.  i386 parameters were copied to 8
other arches verbatim, mostly after they stopped working on i386, and
mostly without the large comment saying how the values were chosen on
i386.  powerpc has a non-verbatim copy which just changes the uncritical
parameter and seems to add a sign extension bug to it.

Just treat negative offsets as offsets if they are no more negative than
-db_offset_max (default -64K), and remove all the broken parameters.

-64K is not very negative, but it is enough for frame and stack pointer
offsets since kernel stacks are small.

The over-engineering was mainly to go more negative than -64K for the
negative offset format, without affecting printing for more than a
single address.

Addresses in the top 64K of a (full 32-bit or 64-bit) address space
are now printed less well, but there aren't many interesting ones.
For arches that have many interesting ones very near the top (e.g.,
68k has interrupt vectors there), there would be no good limit for
the negative offset format and -64K is a good as anything.
2017-03-26 18:46:35 +00:00
Ruslan Bukin
43b595f6a5 Implement atomic_fcmpset_*() for RISC-V.
Requested by: mjg
Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D9447
2017-02-05 00:32:12 +00:00
Konstantin Belousov
9fb10d635e Define the vm_ooffset_t and vm_pindex_t types as machine-independend.
The types are for the byte offset and page index in vm object.  They
are similar to off_t, which is defined as 64bit MI integer.  Using MI
definitions will allow to provide consistent MD values of vm
object-related maximum sizes.

Reviewed by:	alc
Sponsored by:	The FreeBSD Foundation
MFC after:	1 week
2017-02-04 12:26:38 +00:00
Li-Wen Hsu
8ff21c23a5 Add RISC-V support for truss(1)
While here, extract NARGREG as a definition.

Reviewed by:	br
Differential Revision:	https://reviews.freebsd.org/D9249
2017-01-24 09:41:44 +00:00
Ruslan Bukin
250b1bf3c5 Disable superpages reservations as we don't have implemented them yet.
Requested by:	Alan Cox <alc@rice.edu>
Sponsored by:	DARPA, AFRL
2016-11-21 12:00:31 +00:00
Ruslan Bukin
7804dd5212 Add full softfloat and hardfloat support for RISC-V.
Hardfloat is now default (use riscv64sf as TARGET_ARCH
for softfloat).

Sponsored by:	DARPA, AFRL
Differential Revision:	https://reviews.freebsd.org/D8529
2016-11-16 15:21:32 +00:00
Ruslan Bukin
2ad1d09f16 o Add support for long double.
o Add support for latest RISC-V GNU toolchain.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-11-03 13:06:17 +00:00
Warner Losh
b2a7ac4802 Fix building on i386 and arm. But 'public domain' headers on the files
with no creative content. Include "lost" changes from git:
o Use /dev/efi instead of /dev/efidev
o Remove redundant NULL checks.

Submitted by: kib@, dim@, zbb@, emaste@
2016-10-13 06:56:23 +00:00
Warner Losh
943ac2b07e Include stubs even on the platforms we don't support so libsysdecode
continues to build.
2016-10-11 22:54:29 +00:00
Ruslan Bukin
5f8228b2f3 o Remove operation in machine mode.
Machine privilege level was specially designed to use in vendor's
  firmware or bootloader. We have implemented operation in machine
  mode in FreeBSD as part of understanding RISC-V ISA, but it is time
  to remove it.
  We now use BBL (Berkeley Boot Loader) -- standard RISC-V firmware,
  which provides operation in machine mode for us.
  We now use standard SBI calls to machine mode, instead of handmade
  'syscalls'.
o Remove HTIF bus.
  HTIF bus is now legacy and no longer exists in RISC-V specification.
  HTIF code still exists in Spike simulator, but BBL do not provide
  raw interface to it.
  Memory disk is only choice for now to have multiuser booted in Spike,
  until Spike has implemented more devices (e.g. Virtio, etc).

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-08-10 12:41:36 +00:00
Ruslan Bukin
98f50c44e3 Update RISC-V port to Privileged Architecture Version 1.9.
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-08-02 14:50:14 +00:00
Ruslan Bukin
e933649fb9 Remove duplicate define. 2016-06-08 13:57:18 +00:00
Ruslan Bukin
6f397ac71b Increase the size and alignment of the setjmp buffer.
This is required for future CPU extentions.

Reviewed by:	brooks
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-05-26 10:03:30 +00:00
Ruslan Bukin
fed1ca4b71 Add initial DTrace support for RISC-V.
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-05-24 16:41:37 +00:00
Ruslan Bukin
9af9422682 Rework the list of all pmaps: embed the list link into pmap. 2016-04-26 14:38:18 +00:00
Ruslan Bukin
00106e52c2 Add the non-standard "IO interrupt" vector used by lowRISC.
For now they provide UART irq only.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-26 12:56:44 +00:00
Ruslan Bukin
30b72b6871 Move arm's devmap to some generic place, so it can be used
by other architectures.

Reviewed by:	imp
Differential Revision:	https://reviews.freebsd.org/D6091
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-26 11:53:37 +00:00
Ruslan Bukin
02a371289a o Implement shared pagetables and switch from 4 to 3 levels page
memory system.

RISC-V ISA has only single page table base register for both kernel
and user addresses translation. Before this commit we were using an
extra (4th) level of pagetables for switching between kernel and user
pagetables, but then realized FPGA hardware has 3-level page system
hardcoded. It is also become clear that the bitfile synthesized for
4-level system is untested/broken, so we can't use extra level for
switching.

We are now share level 1 of pagetables between kernel and user VA.
This requires to keep track of all the user pmaps created and once we
adding L1 page to kernel pmap we have to add it to all the user pmaps.

o Change the VM layout as we must have topmost bit to be 1 in the
  selected page system for kernel addresses and 0 for user addresses.
o Implement pmap_kenter_device().
o Create the l3 tables for the early devmap.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-04-25 14:47:51 +00:00
Ruslan Bukin
d52d6d7ca7 Add support for ddb(4).
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-03-10 15:51:43 +00:00
Ruslan Bukin
14232d424d o Use uint64_t for page number as it doesn't fit uint32_t.
o Implement growkernel bits for L1 level of pagetables.

This allows us to boot with 128GB of physical memory.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-26 14:04:00 +00:00
Ruslan Bukin
17696c12f5 Add support for symmetric multiprocessing (SMP).
Tested on Spike simulator with 2 and 16 cores (tlb enabled),
so set MAXCPU to 16 at this time.

This uses FDT data to get information about CPUs
(code based on arm64 mp_machdep).

Invalidate entire TLB cache as it is the only way yet.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-24 16:50:34 +00:00
Ruslan Bukin
c7977d4cee Remove duplicates. 2016-02-22 14:13:05 +00:00
Ruslan Bukin
229f3f0d9c Increase kernel and user VA space.
This allows us to boot with more than 128MB of physical memory.

Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
2016-02-18 15:28:57 +00:00
Ruslan Bukin
5fe191b01e Add the implementation of atomic_swap_32(). 2016-02-17 14:32:03 +00:00
Ruslan Bukin
f936aa4a3a Use better form representing 32 x 128-bit floating-point registers.
Suggested by:	kib
2016-02-17 14:24:25 +00:00
Ruslan Bukin
f3d389ee9e Use __uint64_t type for floating point registers
as compiler don't know about __uint128_t yet.

Discussed with:	theraven, kib
2016-02-12 14:29:14 +00:00
Ruslan Bukin
e3ee7f49f1 Access pcpup using gp register. 2016-02-04 14:30:46 +00:00
Ruslan Bukin
4d50647d52 Reuse gp register for pcpu pointer.
gp (global pointer) is used by compiler in userland only,
so re-use it for pcpup in kernel, save it on stack on switching
out to userland and load back on return to kernel.

Discussed with:	jhb, andrew, kib
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D5178
2016-02-04 12:49:28 +00:00
Ruslan Bukin
02568041ed Correct RISC-V exception types. 2016-01-18 17:49:32 +00:00
Ruslan Bukin
8d7e7a98db Import RISC-V machine headers. This is a minimal set required to compile
kernel and userland.

Reviewed by:	andrew, imp, kib
Sponsored by:	DARPA, AFRL
Sponsored by:	HEIF5
Differential Revision:	https://reviews.freebsd.org/D4554
2015-12-17 18:44:30 +00:00