DPCPU area was not properly mapped into kernel VA space, which caused page
fault on the first DPCPU access. This patch fixes the problem by mapping DPCPU
area into kernel VA space.
Submitted by: Michal Hajduk, Piotr Ziecik
Reviewed by: cognet, stas
Approved by: re (kib)
Obtained from: Semihalf
- Modules and kernel code alike may use DPCPU_DEFINE(),
DPCPU_GET(), DPCPU_SET(), etc. akin to the statically defined
PCPU_*. Requires only one extra instruction more than PCPU_* and is
virtually the same as __thread for builtin and much faster for shared
objects. DPCPU variables can be initialized when defined.
- Modules are supported by relocating the module's per-cpu linker set
over space reserved in the kernel. Modules may fail to load if there
is insufficient space available.
- Track space available for modules with a one-off extent allocator.
Free may block for memory to allocate space for an extent.
Reviewed by: jhb, rwatson, kan, sam, grehan, marius, marcel, stas
so that it isn't exposured unless needed. In particular this means
that it's easier to tune the memory layout based on board details.
While here, remove inclusion of <machine/intr.h> from mvreg.h. This
also contains exposure to SoC specifics in MI drivers, because NIRQ
depends on the SoC.
the implementation can guarantee forward progress in the event of
a stuck interrupt or interrupt storm. This is especially critical
for fast interrupt handlers, as they can cause a hard hang in that
case. When first called, arm_get_next_irq() is passed -1.
Obtained from: Juniper Networks, Inc.
- Provide dedicated rmans for MEM and IO resources.
- Convert PCI IRQ routing info into a table (from callback approach), provide
config data for alternative DB- boards.
- Fix a wrong boundary check error in pcib_mbus_init_bar()
Obtained from: Semihalf
- Allow for setting per platform MPP/GPIO configuration in the kernel, so
that we can override all settings firmware might set.
- Set decode windows for the remaining on-chip peripherals: CESA, SATA and XOR.
- Improve handling of USB controllers so that all port are available on the
given SOC/platform (e.g. up to three on DB-78xxx), this includes rework of
USB decode windows set-up.
- Other minor fixes and cosmetics.
Obtained from: Semihalf
- Clean up TCLK handling so that it's dynamically recognized depending on
registers settings or chip version/revision. Update registers definitions.
- Teach SOC ident routine about A0 (initial silicon version for general
audience)
Obtained from: Marvell, Semihalf
* Orion
- 88F5181
- 88F5182
- 88F5281
* Kirkwood
- 88F6281
* Discovery
- MV78100
The above families of SOCs are built around CPU cores compliant with ARMv5TE
instruction set architecture definition. They share a number of integrated
peripherals. This commit brings support for the following basic elements:
* GPIO
* Interrupt controller
* L1, L2 cache
* Timers, watchdog, RTC
* TWSI (I2C)
* UART
Other peripherals drivers will be introduced separately.
Reviewed by: imp, marcel, stass (Thanks guys!)
Obtained from: Marvell, Semihalf
