the device is not actually present), clear the corresponding bit in
the ch->devices bitmap. This resolves a panic that occurred with ATAPI/CAM
after an APM suspend/resume, when the ATA hardware would erroneously
report an extra ATAPI device.
Approved by: re, sos
Reviewed by: roberto
MFC after: 7 days
version, plus add support for the new features found in the Rev B
version of the chip. The changelog is quite long and can be provided
on request. Major features include vastly improved protocol violation
handling, full support for the 7902 Rev B, better parity error
handling, and better packetized overrun handling, to name a few.
Approved by: re (blanket)
HP -> CPQ
Rearrange IDs to better match which chips they use.
Convert to uniform product description strings.
Simplify 7901A setup function.
Add the NONPACKFIFO_BUG and PACED_NEGTABLE_BUG entries
for the A.
Add rev B bugs and features.
The double write workaround for CURRSCB is only required if
abort pending is set. Remove this work around and set the
abort pending bug bit on the B at least until we have better
confirmation that the double write is always safe.
Add updated H2B identifiers
Move IOCell paramters into softc and add a hook for the
OSM to modify these as well as other settings prior to
committing them to the chip.
SLEW -> SLEWRATE
PREQDIS in DEVCONFIG1 went away after the A2.
Remove all code that references this bit. This
is especially important since this bit was reused
in the B for a different HW fix workaround.
Properly set the AHD_NEW_IOCELL_OPTS and
AHD_NEW_DFCNTRL_OPTS features for the B.
Remove stray/random extra 7901A generic PCI
table entry. Also switch the correct 7901A
generic entry to use ID_ALL_MASK since we
can only differentiate the 7901A from the
7902 by checking for a "type field" of 0xE.
Set AHD_INTCOLLISIONT_BUG for the Rev B.
Set the PREQDIS bit in DEVCONFIG1 for the B. The
bit is misnamed, but seems to disable a work-around
that breaks on the B on PCI busses.
Add a routine for testing memory mapped register access.
This will hopefully detect things like buggy via chipsets
so that the OSM can fallback to using I/O mapped access
when memory mapped I/O simply will not work.
Approved by: re (blanket)
diagnostic "Setting Mode" messages.
Use a read of HCNTRL to flush our write to CLRCMDCMPLT
on the RevB. This allows us to check to see if the sequencer
is paused and to initiate the interrupt collision workaround
without incuring an extra read.
Approved by: re (blanket)
PCI-X only workarounds are automatically masked out
if we are operating in PCI mode.
Make use of ahd_pci_test_register_access()
Approved by: re (blanket)
Move IOCell paramters into softc and add a hook for the
OSM to modify these as well as other settings prior to
committing them to the chip.
Approved by: re (blanket)
in the per-device kthread. This ensures that synchronisation with
mddestroy() succeeds even if the kthread was not waiting in tsleep()
at the time of the wakeup(). Among other things, this fixes the
problem of mdconfig getting stuck when an attempt is made to use a
zero-length file as a vnode-type backing store.
Approved by: re
aic7xxx.c:
aic7xxx.h:
aic7xxx.reg:
aic7xxx.seq:
Bring in the protocol violation handler from the U320
driver and replace the NO_IDENT sequencer interrupt code
with the PROTO_VIOLATION code. Support for this code
required the following changes:
SEQ_FLAGS:
IDENTIFY_SEEN -> NOT_IDENTIFIED
Added NO_CDB_SENT
SCB_CONTROL:
TARGET_SCB == STATUS_RCVD for initiator mode
scb->flags:
Added SCB_TARGET_SCB since we cannot rely on
TARGET_SCB as a target/initiator differentiator
due to it being overloaded in initiator mode to
indicate that status has been received.
aic7xxx.seq:
Move data fifo CLRCHN to mesgin_rdptrs which is a safer
location for doing this operation. This also saves a
sequencer instruction.
aic7xxx.c:
aic7xxx.h:
Change ahc/ahd_upate_neg_request() to take a "negotiation
type" enum that allows us to negotiate:
o only if the goal and current parameters differ.
o only if the goal is non-async
o always - even if the negotiation will be for async.
aic7xxx.seq:
Reset the FIFO whenever a short CDB transfer occurs
so that the FIFO contents do not corrupt a future CDB
transfer retry.
Add support for catching the various protocol violations
handled by ahc_handle_protocol_violation.
Reformat some comments.
aic7xxx.c:
aic7xxx.h:
Just for safety, have the aic7xxx driver probe
the stack depth.
aic7xxx.c:
aic7xxx.h:
Save and restore stack contents during diagnostics.
Some chip variants overwrite stale entries on a
stack "pop".
Don't use 0 to probe the stack depth. 0 is the typical
value used to backfill the stack if entries are overwritten
on a "pop".
aic7xxx.h:
Add a missing typedef.
Collapse SCB flag entries so they are bit contiguous.
Add AHD_ULTRA2_XFER_PERIOD for narrow fallback calculations
aic7xxx.c:
Don't panic (as a diagnostic to catch bugs) if we decided to
force the renegotiation of async even if we believe we are
already async. This should allow us to negotiate async instead
of the full user goal rate during startup if bus resets are
disabled.
Add a space to the end of the ahc/ahd_print_devinfo routines
so that it behaves as expected by the code that uses it.
Only force a renegotiation on a selection timeout
if the SCB was valid. Doing otherwise may be dangerous
as the connection was not valid for an unknown reason.
Add additional diagnostic output to ahc_dump_card_state(),
and have it use the register pretty printing functions.
Update ahc_reg_print() to handle a NULL cur_col.
Add a newline to ahc_dump_card_state() output.
Bring back "use_ppr". We need to use_ppr anytime
doppr is true or we have non-zero protocol options.
The later case was not handled in the recent removal
of use_ppr.
Move a comment and remove a useless clearing of use_ppr.
Don't disable ENBUSFREE when single stepping on
a DT capable controller. We cannot re-enable unexpected
busfree detection, so we must clear BUSFREE on each
step instead.
Correct the lookup of the SCB ID in ahc_handle_proto_error.
Remove a diagnostic printf.
Remove unecessary restoration of the STACK for older
chips.
Approved by: re (blanket)
This will hopefully detect things like buggy via chipsets
so that the OSM can fallback to using I/O mapped access
when memory mapped I/O simply will not work.
Approved by: re (blanket)
AHC_ALLOW_MEMIO is set, or the hint hint.ahc.N.allow_memio=1 is
set in the bootloader.
Make use of ah?_pci_test_register_access().
Approved by: re (blanket)
o Add needed headers.
o Add stg_products[] product data and stg_match() function.
o Change stg_pccard_method[] to support both OLDCARD and NEWCARD.
Approved by: re
o Add needed headers.
o Add ncv_products[] product data and ncv_match() function.
o Change ncv_pccard_method[] to support both OLDCARD and NEWCARD.
Suggestion for REX-5572 matching part by imp.
Approved by: re
o Add needed headers.
o Add nsp_producs[] product data and nsp_match() function.
o Change nsp_pccard_method[] to support both OLDCARD and NEWCARD.
o Add warning to fall back to PIO mode when it cannot use SMIT mode.
This is needed because memories are not allocated with NEWCARD now.
Submitted by: takawata
Approved by: re
or stg driver. They are,
Macnica mPS110, PANASONIC(KME) KXLC004, Qlogic Fast SCSI,
Workbit Ultra Ninja-16, (ID based)
Future Domain SCSI2GO, IBM SCSI PCMCIA card, I-O DATA CBSC16,
Macnica mPS100, Newmedia BASICS-SCSI, RATOC REX-5536, RATOC REX-5536AM,
RATOC REX-5536M, RATOC REX5572, Workbit NinjaSCSI-3
(CIS based)
Note: We need vendor IDs WORKBIT2 and IODATA3 which is -1, since some
cards does not have IDs in the CIS and fails to be probed without
this fake vendor IDs.
o Change the strings of RATOC REX_R280 from REX-R280 to REX-R280/REX-9530.
This reminds us that REX-R280 and REX-R9530 have same ID (same product).
Reviewed by: imp
Approved by: re
Obtained from: /etc/defaults/pccard.conf,
List of CIS tupples by Toshihiko ARAI and PAO project:
http://www.linkclub.or.jp/~clover/cis/
Change suggestion by: HASEGAWA Tomoki <thasegawa@mta.biglobe.ne.jp>
for I-O DATA CBSC16 entry
There were no serious problem reports on this in spite of my concern.
To get debug output from acpi_pci_link, just enable bootverbose flag
in usual manner (boot -v).
Approved by: re
aicasm_gram.y:
Use a direct move from allzeros to emulate a
mvi of 0.
aicasm_insformat.h:
sync $Id$
aicasm_symbol.c:
Minor header change.
Approved by: re (blanket)
pci_get_ether accesor, which gets it from the CIS for cardbus cards
(and from other pci-like buses via whatever mechanism is used there).
Submitted by: sam
Approved by: re (blanket)
sometimes, so return it when requested and it does. Also a little
more infrastructure for a few other things.
Submitted by: sam
Approved by: re (blanket for NEWCARD)
buses support querying the MAC address in a standard-for-that-bus way.
The base pci bus returns NULL for this IVAR always.
Submitted by: sam
Approved by: re (blanket for NEWCARD)
- If a PCI device is not present, then a 32-bit read_config() is going to
return 0xffffffff not 0xffff.
- For the 82454NX chipset, the MIOC that we read the bus numbers of the
various host-PCI bridges from is at function (slot) 0x10 not 0x0.
Approved by: re (rwatson)
1. Detect the revision of the Rhine chip we're using.
2. Use the force reset command on revisions which support
it whenever the normal reset command fails.
This should solve a wide range of "my vr0 locks up with reset
failed messages" problems. (Although the root causes should
be eventually tracked down.)
Tested by: grenville armitage <garmitage@swin.edu.au>
Obtained from: Via's if_fet driver
MFC after: 3 days
Approved by: re
If the value from the user is less than 177, assume it is a multiple of
a single speed CDROM and convert to KB/sec.
No complaints from: sos
Reviewed by: ken
Approved by: re
MFC after: 1 day
to PCI bridge can be read be evaluating the _BBN method of the host to PCI
device. Unfortunately, there appear to be some lazy/ignorant/moronic/
whatever BIOS writers that return 0 for _BBN for all host to PCI bridges in
the system. On a system with a single host to PCI bridge this is not a
problem as the child bus of that single bridge will be bus 0 anyway.
However, on systems with multiple host to PCI bridges and l/i/m/w BIOS
writers this is a major problem resulting in all but the first host to
PCI bridge failing to attach. So, this adds a workaround.
If the _BBN of a host to PCI bridge is zero and pcib0 already exists
and is not us, the we use _ADR to look up our PCI function and slot
(we currently assume we are on bus 0) and use that to call
host_pcib_get_busno() to try and extract our bus number from config
registers on the host to PCI bridge device. If that fails, then we make
an evil assumption that ACPI's _SB_ namespace lays out the host to PCI
bridges in ascending order and use our pcib unit number as our bus
number.
Approved by: re
after configure() has run. Only create the device if ofwcons is the
highest priority console. Make a dev alias with the same name as the
firmware output-device property.
trigger a breakpoint with this chip.
- Fiddle the right bits in the cn input and output routines to disable port
interrupts and enable visibility of the masked interrupt status bits.
- Register a shutdown final event handler to put the chip back in the mode
that the prom expects.
