Do not map the trap vectors into the kernel's address space. They are
only used in real mode and keeping them mapped only serves to make NULL
a valid address, which results in silent NULL pointer deferences.
Suggested by: Patrick Kerharo
Obtained from: projects/ppc64
Add sysctls in ahd(4) in order to keep track of different classes of
errors. So far 3 different classes are present (correctable,
uncorrectable and fatal) but more can be added easilly.
Sponsored by: Sandvine Incorporated
Add the possibility for vfs.root.mountfrom tunable to accept a list of
items rather than a single one.
While there fix also a nit in a comment.
Sponsored by: Sandvine Incorporated
Provide an effective (relocated) address when building modules metadata.
This lets modules loaded dynamically in loader(8) work for U-Boot-based
platforms.
- U-Boot support library for loader(8) (ARM, PowerPC)
- multiprocessor (SMP) (PowerPC)
- E500 (Book-E) embedded CPU support (PowerPC)
- Freescale PowerQUICCIII MPC85xx system-on-chip support (single-
and dual-core) (PowerPC)
- Feroceon, Sheeva embedded CPU support
- Marvell Orion (88F5281), Kirkwood (88F6281) and Discovery
Innovation (MV-78100) systems-on-chip support (ARM)
- DS133x and DS1553 RTC support
- tsec(4) Gigabit Ethernet driver
- mge(4) Gigabit Ethernet driver
- kernel core dump support (PowerPC)
- mini dump support (ARM)
- gdbserver(1) support for (ARM, PowerPC)
Submitted by: raj
Fix parsing of mount options specified with -o in case an option with
value is preceded by an option without value (for example -o
option1,option2=value). Options must be separated before searching for
'='. Also compare pnextopt explicitly against NULL.
PR: bin/134069
Approved by: trasz (mentor)
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Introduce hw.hptrr.attach_generic loader tunable to deny hptrr driver
attach chips with generic Marvell (non-HighPoint) PCI identification.
These chips are also supported by ata(4). Some vendors, like Supermicro,
are using same chips without providing HPT RAID BIOS.
PR: kern/120842, kern/136750
Core2Duo/Core2Quad CPUs are unable to control frequency of single CPU
core, only pair of them. As result, both cores are running on highest
one of requested frequencies, and that is reported by status register.
Such behavior confuses frequency validation logic, as it runs on only
one core, as SMP is not yet launched, making EIST completely unusable.
Disable frequency validation by default, for systems with more then one
CPU, until we can implement it properly. It looks like making more harm
now then benefits. Add 'hw.est.strict' loader tunable to control it.
PR: amd64/140506
Fix Intel PATA UDMA timings setting, affecting write performance.
Binary divider value 10 specified in datasheet is not a hex 0x10.
UDMA2 should be 33/2 instead of 66/4, which is documented as reverved,
UDMA4 should be 66/2 instead of 66/4, which is definitely wrong.
Release over-agressive WDMA0 mode timings as close to spec as chip can.
Use only lower byte of sectors_intr IDENTIFY word as sector count.
This fixes SET_MULTI error during boot on devices supporting less then
16 sectors per interrupt.
Do not attach JMicrons with single PCI function. They are not working as
AHCI for some reason, even when declaring so. Let atajmicron configure
them for us and provide PATA support.
Correct the information about the doceng@ team members - Murray Stokely
stepped down some time ago, about the same time as Giorgos Keramidas
joined the team.
PR: 140465
Submitted by: Denny Lin <dennylin93@cnmc32.hs.ntnu.edu.tw>
Unroll copying of the registers in {g,s}et_mcontext() and limit it
to the set actually restored by tl0_ret() instead of using the whole
trapframe. Additionally skip %g7 as that register is used as the
userland TLS pointer.
PR: 140523
Fix an obvious panic by not casting from a pointer that is 4-bytes
alignment to a type that needs 8-byte alignment, and thus causing
misaligned memory references.
o Align function on a 32-byte boundary so that the core's front-end
can deliver 2 bundles per cycle to the back-end.
o Mark syscall stubs with a special unwind ABI tag so that unwind
libraries know how to unwind.
Disable PortMultiplier Async Notifications for time of ports reset.
They are useless at that time, but confuse Marvell AHCI.
Add quirk for SiI57XX Port Multipliers, to hide extra port.
- Add some bits of HDMI/DisplayPort support from later specification updates.
It may be not enough to make them work, but at least should give some
information about these beasts.
- Add Realtek ALC887 codec ID.
Change the way in which AHCI+PATA combined controllers, such as JMicron
are handled. Instead of trying to attach two different drivers to
single device, wrapping each call, make one of them (atajmicron)
attach do device solely, but create child device for AHCI driver,
passing it all required resources. It is quite easy, as none of
resources are shared, except IRQ.
Add support for AHCI SATA parts of alike SATA+PATA MArvell controllers.
Add IDs of Marvell 88SX6102, 88SX6111. 88SX6141 controllers.
As result, it:
- makes drivers operation more independent and straitforward,
- allows to use new ahci(4) driver with such devices, adding support for
new features, such as PMP and NCQ, same time keeping legacy PATA support,
- will allow to just drop old ataahci driver, when it's time come.
- Remove most of direct relations between ATA(4) peripherial and controller
levels. It makes logic more transparent and is a mandatory step to wrap
ATA(4) controller level into ATA-native CAM SIM.
- Tune AHCI and SATA2 SiI drivers memory allocation a bit to allow bigger
I/O transaction sizes without additional cost.
- Add unit to the short month names for Japanese locales.
Without unit, the output of the application like ls(1)
is complicated.
- Since %b contains unit, %b is not suitable for c_fmt,
now. Use %_m instead.
