Commit Graph

115 Commits

Author SHA1 Message Date
Pyun YongHyeon
caa19d50d1 Add new device id of D-Link DGE-530T Rev. C controller. DGE-503T
Rev A1 and B1 is supported by sk(4) but the DGE-530T Rev. C
controller is re-branded RealTek 8169 controller.

PR:	kern/159116
Approved by:	re (kib)
2011-07-30 01:06:12 +00:00
Pyun YongHyeon
39e692013a Add initial support for RTL8401E PCIe Fast Ethernet.
PR:	154789
2011-02-16 21:59:42 +00:00
Pyun YongHyeon
54899a96e1 Add support for RTL8105E PCIe Fast Ethernet controller. It seems
the controller has a kind of embedded controller/memory and vendor
applies a large set of magic code via undocumented PHY registers in
device initialization stage. I guess it's a firmware image for the
embedded controller in RTL8105E since the code is too big compared
to other DSP fixups. However I have no idea what that magic code
does and what's purpose of the embedded controller. Fortunately
driver seems to still work without loading the firmware.

While I'm here change device description of RTL810xE controller.

H/W donated by:	Realtek Semiconductor Corp.
2011-01-26 21:14:20 +00:00
Pyun YongHyeon
502be0f749 Do not use interrupt taskqueue on controllers with MSI/MSI-X
capability. One of reason using interrupt taskqueue in re(4) was
to reduce number of TX/RX interrupts under load because re(4)
controllers have no good TX/RX interrupt moderation mechanism.
Basic TX interrupt moderation is done by hardware for most
controllers but RX interrupt moderation through undocumented
register showed poor RX performance so it was disabled in r215025.
Using taskqueue to handle RX interrupt greatly reduced number of
interrupts but re(4) consumed all available CPU cycles to run the
taskqueue under high TX/RX network load.  This can happen even with
RTL810x fast ethernet controller and I believe this is not
acceptable for most systems.

To mitigate the issue, use one-shot timer register to moderate RX
interrupts. The timer register provides programmable one-shot timer
and can be used to suppress interrupt generation. The timer runs at
125MHZ on PCIe controllers so the minimum time allowed for the
timer is 8ns. Data sheet says the register is 32 bits but
experimentation shows only lower 13 bits are valid so maximum time
that can be programmed is 65.528us. This yields theoretical maximum
number of RX interrupts that could be generated per second is about
15260. Combined with TX completion interrupts re(4) shall generate
less than 20k interrupts. This number is still slightly high
compared to other intelligent ethernet controllers but system is
very responsive even under high network load.

Introduce sysctl variable dev.re.%d.int_rx_mod that controls amount
of time to delay RX interrupt processing in units of us. Value 0
completely disables RX interrupt moderation. To provide old
behavior for controllers that have MSI/MSI-X capability, introduce
a new tunable hw.re.intr_filter. If the tunable is set to non-zero
value, driver will use interrupt taskqueue. The default value of
the tunable is 0. This tunable has no effect on controllers that
has no MSI/MSI-X capability or if MSI/MSI-X is explicitly disabled
by administrator.

While I'm here cleanup interrupt setup/teardown since re(4) uses
single MSI/MSI-X message at this moment.
2011-01-26 20:25:40 +00:00
Pyun YongHyeon
d180a66f19 Remove TX taskqueue and directly invoke re_start in interrupt task. 2011-01-25 23:27:28 +00:00
Pyun YongHyeon
4a58fd452a Prefer MSI-X to MSI on controllers that support MSI-X. All
recent PCIe controllers(RTL8102E or later and RTL8168/8111C or
later) supports either 2 or 4 MSI-X messages. Unfortunately vendor
did not publicly release RSS related information yet. However
switching to MSI-X is one-step forward to support RSS.
2011-01-25 22:18:00 +00:00
Pyun YongHyeon
ef278cb4ae Change model names of controller RTL_HWREV_8168_SPIN[123] to real ones.
s/RL_HWREV_8168_SPIN1/RL_HWREV_8168B_SPIN1/g
s/RL_HWREV_8168_SPIN2/RL_HWREV_8168B_SPIN2/g
s/RL_HWREV_8168_SPIN3/RL_HWREV_8168B_SPIN3/g
No functional changes.
2011-01-18 00:46:10 +00:00
Pyun YongHyeon
81eee0ebf8 Implement initial jumbo frame support for RTL8168/8111 C/D/E PCIe
GbE controllers. It seems these controllers no longer support
multi-fragmented RX buffers such that driver have to allocate
physically contiguous buffers.

 o Retire RL_FLAG_NOJUMBO flag and introduce RL_FLAG_JUMBOV2 to
   mark controllers that use new jumbo frame scheme.
 o Configure PCIe max read request size to 4096 for standard frames
   and reduce it to 512 for jumbo frames.
 o TSO/checksum offloading is not supported for jumbo frames on
   these controllers. Reflect it to ioctl handler and driver
   initialization.
 o Remove unused rl_stats_no_timeout in softc.
 o Embed a pointer to structure rl_hwrev into softc to keep track
   of controller MTU limitation and remove rl_hwrev in softc since
   that information is available through a pointer to structure
   rl_hwrev.

Special thanks to Realtek for donating sample hardwares which made
this possible.

H/W donated by:	Realtek Semiconductor Corp.
2011-01-17 03:24:33 +00:00
Pyun YongHyeon
f0431c5bb0 Add initial support for RTL8168E/8111E-VL PCIe GbE.
H/W donated by:	Realtek Semiconductor Corp.
2011-01-17 02:23:50 +00:00
Pyun YongHyeon
d6d7d923ad Implement TSO on RealTek RTL8168/8111 C or later controllers.
RealTek changed TX descriptor format for later controllers so these
controllers require MSS configuration in different location of TX
descriptor. TSO is enabled by default for controllers that use new
descriptor format.
For old controllers, TSO is still disabled by default due to broken
frames under certain conditions but users can enable it.
Special thanks to Hayes Wang at RealTek.

MFC after:	2 weeks
2011-01-10 23:28:46 +00:00
Pyun YongHyeon
45b8980f0e Remove standard PCI configuration space register definitions. 2010-11-08 22:10:51 +00:00
Pyun YongHyeon
19c54b5168 Remove trailing white spaces. 2010-11-08 22:05:11 +00:00
Pyun YongHyeon
314dfe2b28 Consistently use tab character instead of using space character.
No functional changes.
2010-11-08 22:03:40 +00:00
Pyun YongHyeon
483cc44070 Follow the lead of vendor's interrupt moderation mechanism.
It seems RTL8169/RTL8168/RTL810xE has a kind of interrupt
moderation mechanism but it is not documented at all. The magic
value dramatically reduced number of interrupts without noticeable
performance drops so apply it to all RTL8169/RTL8169 controllers.
Vendor's FreeBSD driver also applies it to RTL810xE controllers but
their Linux driver explicitly cleared the register, so do not
enable interrupt moderation for RTL810xE controllers.

While I'm here sort 8169 specific registers.

Obtained from:	RealTek FreeBSD driver
2010-11-08 21:50:50 +00:00
Pyun YongHyeon
0534aae0ce Add simple MAC statistics counter reading support. Unfortunately
useful counters like rl_missed_pkts is 16 bits quantity which is
too small to hold meaningful information happened in a second. This
means driver should frequently read these counters in order not to
lose accuracy and that approach is too inefficient in driver's
view. Moreover it seems there is no way to trigger an interrupt to
detect counter near-full or wraparound event as well as lacking
clearing the MAC counters. Another limitation of reading the
counters from RealTek controllers is lack of interrupt firing at
the end of DMA cycle of MAC counter read request such that driver
have to poll the end of the DMA which is a time consuming process
as well as inefficient. The more severe issue of the MAC counter
read request is it takes too long to complete the DMA. All these
limitation made maintaining MAC counters in driver impractical. For
now, just provide simple sysctl interface to trigger reading the
MAC counters. These counters could be used to track down driver
issues. Users can read MAC counters maintained in controller with
the following command.
#sysctl dev.re.0.stats=1

While I'm here add check for validity of dma map and allocated
memory before unloading/freeing them.

Tested by:	rmacklem
2010-11-05 19:28:00 +00:00
Pyun YongHyeon
4702e878b7 Consistently use capital letters. 2010-04-09 23:00:24 +00:00
Pyun YongHyeon
d0c4515667 Add preliminary support for 8168E/8111E PCIe controller.
While I'm here simplify device description string.

Tested by:	Michael Beckmann < michael <> apfel dot de >
MFC after:	5 days
2010-04-09 22:50:28 +00:00
Pyun YongHyeon
8281a098c6 Add initial support for RTL8103E PCIe fastethernet.
PR:	kern/142974
2010-01-27 17:49:27 +00:00
Pyun YongHyeon
5fa06abe89 Add RTL8168DP/RTL8111DP device id. While I'm here append "8111D" to
the description of RTL8168D as RL_HWREV_8168D can be either
RTL8168D or RTL8111D.

PR:	kern/137672
MFC after:	3 days
2009-08-24 18:58:13 +00:00
Tai-hwa Liang
3d22427cff Adding hardware ID for RTL810x PCIe found on HP Pavilion DV2-1022AX.
Reviewed by:	yongari
Approved by:	re (kib, kensmith)
2009-07-14 04:35:13 +00:00
Pyun YongHyeon
f2e491c9c5 For RTL8139C+ controllers, have controller handle padding short
checksum offload frames. Software workaround used for broken
controllers(RTL8169, RTL8168, RTL8168B) seem to cause watchdog
timeouts on RTL8139C+.
Introduce a new flag RL_FLAG_AUTOPAD to mark automatic padding
feature of controller and set it for RTL8139C+ and controllers that
use new descriptor format. This fixes watchdog timeouts seen on
RTL8139C+.

Reported by:	Dimitri Rodis < DimitriR <> integritasystems dot com >
Tested by:	Dimitri Rodis < DimitriR <> integritasystems dot com >
2009-04-20 07:13:04 +00:00
Pyun YongHyeon
f1bb696a81 Allocating 2 MSI messages do not seem to work on certain controllers
so use just 1 MSI message. This fixes regression introduced in
r188381.

Tested by:	many
2009-02-11 00:23:56 +00:00
Jung-uk Kim
566ca8ca5d - Add support for 8110SCe part. Some magic registers were taken from
Linux driver.
- Swap hardware revisions for 8110S and 8169S as Linux driver claims.

Reviewed by:	yongari (early version)
2009-01-20 20:22:28 +00:00
Jung-uk Kim
aaab4fbea7 Retire RL_FLAG_INVMAR bit to match its comment and reality. 2009-01-20 20:04:09 +00:00
Pyun YongHyeon
96b774f489 Sometimes RTL8168B seems to take long time to access GMII registers
in device attach phase. Double GMII register access timeout value
to fix the issue.

Reported by:	wkoszek
Tested by:	wkoszek
2009-01-19 02:31:27 +00:00
Pyun YongHyeon
818951afd8 It seems that RealTek PCIe controllers require an explicit Tx poll
command whenever Tx completion interrupt is raised. The Tx poll
bit is cleared when all packets waiting to be transferred have been
processed. This means the second Tx poll command can be silently
ignored as the Tx poll bit could be still active while processing
of previous Tx poll command is in progress.
To address the issue re(4) used to invoke the Tx poll command in Tx
completion handler whenever it detects there are pending packets in
TxQ. However that still does not seem to completely eliminate
watchdog timeouts seen on RealTek PCIe controllers. To fix the
issue kick Tx poll command only after Tx completion interrupt is
raised as this would indicate Tx is now idle state such that it can
accept new Tx poll command again. While here apply this workaround
for PCIe based controllers as other controllers does not seem to
have this limitation.

Tested by:	Victor Balada Diaz < victor <> bsdes DOT net >
2008-12-17 08:18:11 +00:00
Pyun YongHyeon
61f45a7222 For RTL8168C SPIN2 controllers, make sure to take the controller
out of sleep mode prior to accessing to PHY. This should fix device
attach failure seen on these controllers. Also enable the sleep
mode when device is put into sleep state.

PR:	kern/123123, kern/123053
2008-12-17 06:01:03 +00:00
Pyun YongHyeon
886ff602f2 Make WOL work on RTL8168B. This controller seems to require
explicit command to enable Rx MAC prior to entering D3.

Tested by:	Cyrus Rahman <crahman <> gmail DOT com>
2008-12-11 02:24:11 +00:00
Pyun YongHyeon
0596d7e65d Don't access undocumented register 0x82 on controllers that
have no such register. While here clear undocumented PHY
register 0x0B for RTL8110S.

Obtained from:	RealTek FreeBSD driver
2008-12-11 01:41:38 +00:00
Pyun YongHyeon
ead8fc669e Newer RealTek controllers requires setting stop request bit to
terminate active Tx/Rx operation.
2008-12-11 01:26:18 +00:00
Pyun YongHyeon
130b6dfb35 o Implemented miibus_statchg handler. It detects whether re(4)
established a valid link or not. In miibus_statchg handler add a
  check for established link is valid one for the controller(e.g.
  1000baseT is not a valid link for fastethernet controllers.)
o Added a flag RE_FLAG_FASTETHER to mark fastethernet controllers.
o Added additional check to know whether we've really encountered
  watchdog timeouts or missed Tx completion interrupts. This change
  may help to track down the cause of watchdog timeouts.
o In interrupt handler, removed a check for link state change
  interrupt. Not all controllers have the bit and re(4) did not
  rely on the event for a long time. In addition, re(4) didn't
  request the interrupt in RL_IMR register.

Tested by:	rpaulo
2008-12-08 02:34:13 +00:00
Pyun YongHyeon
59ef640d9e Add 8168D support.
Submitted by:	Andrew < andrewwtulloch <> gmail DOT com >
2008-12-02 03:39:34 +00:00
Warner Losh
4a8cdcaf87 Make RL_TWISTER_ENABLE a tunable/sysctl. Eliminate it as an option.
Fix module build.

Submitted by:	Kostik Belousov
2008-11-02 16:50:57 +00:00
Warner Losh
9b27478be4 Add RL_TWISTER_ENABLE option. This enables the magic bits to do long
cable tuning.  This has helped in some installations for hardware
deployed by a former employer.  Made optional because the lists aren't
full of complaints about these cards... even when they were wildly
popular.

Reviewed by:	attilio@, jhb@, trhodes@ (all an older version of the patch)
2008-10-31 23:24:13 +00:00
Pyun YongHyeon
05a8dc6dac Various bus_dma(9) fixes.
- The hardware does not support DAC so limit DMA address space to
   4GB.
 - Removed BUS_DMA_ALLOC_NOW flag.
 - Created separated Tx buffer and Rx buffer DMA tags. Previously
   it used to single DMA tag and it was not possible to specify
   different DMA restrictions.
 - Apply 4 bytes alignment limitation of Tx buffer.
 - Apply 8 bytes alignment limitation of Rx buffer.
 - Tx side bus_dmamap_load_mbuf_sg(9) support.
 - Preallocate Tx DMA maps as creating DMA maps take very long time
   on architectures that require real DMA maps.
 - Adjust guard buffer size to 1522 + 8 as it should include VLAN
   and additional reserved bytes in Rx buffer.
 - Plug memory leak in device detach. Previously wrong buffer
   address was used to free allocated memory.
 - Added rl_list_rx_init() to clear Rx buffer and cleared the
   buffer.
 - Don't destroy DMA maps in rl_txeof() as the DMA map should be
   reused. There is no reason to destroy/recreate the DMA maps in
   this driver.
 - Removed rl_dma_map_rxbuf()/rl_dma_map_txbuf() callbacks.
 - The hardware does not support descriptor based DMA on Tx side
   and the Tx buffer address should be aligned on 4 bytes boundary
   as well as manual padding for short frames. Because of this
   hardware limitation rl(4) always used to invoke m_defrag(9) to
   get a 4 bytes aligned single buffer. However m_defrag(9) takes
   a lot of CPU cycles on slow machines and not all packets need
   the help of m_defrag(9). Armed with the information, don't
   invoke m_defrag(9) if the following conditions are true.
      1. Buffer is not fragmented.
      2. Buffer is aligned on 4 bytes boundary.
      3. Manual padding is not necessary.
      4. Or padding is necessary but upper stack passed a writable
         buffer and the space needed for padding is satisfied.
   This change combined with preallocated DMA maps greatly
   increased Tx performance of driver on sparc64.
 - Moved bus_dmamap_sync(9) in rl_start_locked() to rl_encap() and
   corrected memory synchronization operation specifier of
   bus_dmamap_sync(9).
 - Removed bus_dmamap_unload(9) in rl_stop(). There is no need to
   reload/unload Rx buffer as rl(4) always have to copy from the
   buffer. It just needs proper bus_dmamap_sync(9) calls before
   copying the received frame.

With this change rl(4) should work on systems with more than 4GB
memory.

PR:	kern/128143
2008-10-25 02:36:08 +00:00
Pyun YongHyeon
ae64408754 The number of bits reserved for MSS in RealTek controllers is
11bits. This limits the maximum interface MTU size in TSO case
as upper stack should not generate TCP segments with MSS greater
than the limit. Armed with this information, disable TSO if
interface MTU is greater than the limit.
2008-08-04 02:05:09 +00:00
Pyun YongHyeon
b1d62f0fd7 Add driver support for RTL8102E and RTL8102EL which is the second
generation of RTL810x PCIe fast ethernet controller. Note, Tx/Rx
descriptor format is different from that of first generation of
RTL8101E series. Jumbo frame is not supported for RTL810x
family.

Tested by:	NAGATA Shinya ( maya AT negeta DOT com )
2008-07-09 01:58:18 +00:00
Pyun YongHyeon
715922d73f Add a new RTL8169 variant, 8169SB(L)/8110SB(L).
Reported by:	nork
Tested by:	nork
2008-07-02 08:00:14 +00:00
Pyun YongHyeon
deb5c680bb Add basic support for RTL8168C, RTL8168CP, RTL8111C and RTL8111CP.
ATM Tx/Rx checksum offload is supported but TSO and jumbo frame is
not yet supported. Because these newer controllers use different
descriptor formats, a flag RL_FLAG_DESCV2 flag was introduced to
handle that case in Tx/Rx handler. Also newer controllers seems to
require to not touch 'enable Tx/Rx bit' in RL_CPLUS_CMD register
so don't blindly try to set that bits.

Note, it seems that there is still power-saving related issue where
driver fails to attach PHY. Rebooting seems to fix that issue but
number of required reboots varys.

Many thanks to users that helped during developement. I really
appreciate their patient and test/feedbacks.
2008-07-02 07:54:53 +00:00
Pyun YongHyeon
351a76f9aa Instead of allocating variables for each events/hardware flags, use
a dedicated flag that represents controller capabilities/events.
This will simplify many part of code that requires different
workaround for each controller revisions and will enhance
readability.
While I'm here move PHY wakeup code up before mii_phy_probe() which
seems to help to wake PHY in some cases.
2008-07-02 06:29:43 +00:00
Pyun YongHyeon
ace7ed5dd5 Switch to memory space register mapping over IO space. If that
mapping fails fall back to traditional IO space access.
2008-07-02 05:21:09 +00:00
Remko Lodder
8dce5c1bf6 Add another 8139D variant.
PR:		124622
Submitted by:	Evgeny Zhirnov <jirnov at gmail dot com>
Approved by:	imp (mentor, implicit)
MFC after:	3 days
2008-06-16 18:32:20 +00:00
Pyun YongHyeon
a4148af5f0 Padding more bytes than necessary one broke another variants of
PCIe RealTek chips. Only pad IP packets if the payload is less than
28 bytes.

Obtained from:	NetBSD
PR:		kern/122221
2008-03-31 04:03:14 +00:00
Pyun YongHyeon
03ca7ae8a9 For MSI capable hardwares, enable MSI enable bit in RL_CFG2
register.  If MSI was disabled by hw.re.msi_disable tunable
expliclty clear the MSI enable bit.
2008-03-23 05:31:35 +00:00
Pyun YongHyeon
c1d0b5737f Don't allow jumbo frame on 8139C+ controller.
While I'm here add a check for minimal MTU length.
2008-03-03 03:41:06 +00:00
Pyun YongHyeon
7467bd5370 Implement WOL.
Tested by:	Fabian Keil ( freebsd-listen AT fabienkeli DOT de )
2008-03-03 03:33:58 +00:00
Pyun YongHyeon
d65abd6663 Overhaul re(4).
o Increased number of Rx/Tx descriptors to 256 for 8169 GigEs
  because it's hard to push the hardware to the limit with default
  64 descriptors.
  TSO requires large number of Tx descriptors to pass a full sized
  TCP segment(65535 bytes IP packet) to hardware. Previously it
  consumed 32 Tx descriptors, assuming MCLBYTES DMA segment size,
  to send the TCP segment which means re(4) couldn't queue more
  than two full sized IP packets.
  For 8139C+ it still uses 64 Rx/Tx descriptors due to its hardware
  limitations. With this changes there are (very) small waste of
  memory for 8139C+ users but I don't think it would affect 8139C+
  users for most cases.
o Various bus_dma(9) fixes.
   - The hardware supports DAC so allow 64bit DMA operations.
   - Removed BUS_DMA_ALLOC_NOW flag.
   - Increased DMA segment size to 4096 from MCLBYTES because TSO
     consumes too many descriptors with MCLBYTES DMA segment size.
   - Tx/Rx side bus_dmamap_load_mbuf_sg(9) support. With these
     changes the code is more readable than previous one and got a
     (slightly) better performance as it doesn't need to pass/
     decode arguments to/from callback function.
   - Removed unnecessary callback function re_dmamap_desc() and
     nuked rl_dmaload_arg structure which was used in the callback.
   - Additional protection for DMA map load failure. In case of
     failure reuse current map instead of returning a bogus DMA
     map.
  -  Deferred DMA map unloading/sync operation for maximum
     performance until we really need to load new DMA map. If we
     happen to reuse current map(e.g. input error) there is no need
     to sync/unload/load again.
  -  The number of allowable Tx DMA segments for a mbuf chains are
     now 32 instead of magic nseg value. If the number of available
     Tx descriptors are short enough to send highly fragmented mbuf
     chains an optimized re_defrag() is called to collapse mbuf
     chains which is supposed to be much faster than m_defrag(9).
     re_defrag() was borrowed from ath(4).
   - Separated Rx/Tx DMA tag from a common DMA tag such that Rx DMA
     tag correctly uses DMA maps that were created with DMA alignment
     restriction(8bytes alignments). Tx DMA tag does not have such
     alignment limitation.
   - Added additional sanity checks for DMA ring map load failure.
   - Added additional spare Rx DMA map for graceful handling of Rx
     DMA map load failure.
   - Fixed misused bus_dmamap_sync(9) and added missing
     bus_dmamap_sync(9) in re_encap()/re_txeof()/re_rxeof().
o Enabled TSO again as re(4) have reasonable number of Tx
  descriptors.
o Don't touch DMA address of a Tx descriptor in re_txeof(). It's
  not needed.
o Fix incorrect update of if_ierrors counter. For Rx buffer
  shortage it should update if_qdrops as the buffer is reused.
o Added checks for unsupported H/W revisions and return ENXIO for
  these hardwares. This is required to remove resource allocation
  code in re_probe as other drivers do in device probe routine.
o Modified descriptor index manipulation macros as it's now possible
  to have different number of descriptors for Rx/Tx.
o In re_start, to save a lock operation, use IFQ_DRV_IS_EMPTY before
  trying to invoke IFQ_DRV_DEQUEUE. Also don't blindly call re_encap
  since we already know the number of available Tx descriptors in
  advance.
o Removed RL_TX_DESC_THLD which was used to reserve RL_TX_DESC_THLD
  descriptors in Tx path. There is no such a limitation mentioned in
  8139C+/8169/8110/8168/8101/8111 datasheet and it seems to work ok
  without reserving RL_TX_DESC_THLD descriptors.
o Fix a comment for RL_GTXSTART. The register is 8bits register.
o Added comments for 8169/8139C+ hardware restrictions on descriptors.
o Removed forward declaration for "struct rl_softc", it's not needed.
o Added a new structure rl_txdesc for Tx descriptor managements and
  a structure rl_rxdesc for Rx descriptor managements.
o Removed unused member variable rl_intlock in driver softc. There are
  still several unused member variables which are supposed to be used
  to access hardware statistics counters. But it seems that accessing
  hardware counters were not implemented yet.
2008-01-15 01:10:31 +00:00
Pyun YongHyeon
1acbb78ada Add another RTL8168 revision 3 which is found on RTL8111-GR Gigabit
Ethernet Controller. Multicast filtering wasn't tested and needs more
expore. While I'm here change complex if statements with switch
statement which would improve readability.

Reported by:	Abdullah Ibn Hamad Al-Marri < wearabnet AT yahoo DOT ca >
Tested by:	Abdullah Ibn Hamad Al-Marri < wearabnet AT yahoo DOT ca >
2007-12-08 00:14:09 +00:00
Remko Lodder
0d985fab86 Add the FNW3603TX Planex NIC.
PR:		76081
Approved by:	imp (mentor)
Submitted by:	umi at pocke dot org
MFC After:	3 days
2007-11-26 18:25:07 +00:00
Pyun YongHyeon
5774c5ff93 Add MSI support.
Ever since switching to adaptive polling re(4) occasionally spews
watchdog timeouts on systems with MSI capability. This change is
minimal one for supporting MSI and re(4) also needs MSIX support
for RTL8111C in future. Because softc structure of re(4) is shared
with rl(4), rl(4) was touched to use the modified softc.

Reported by:	cnst
Tested by:	cnst
Approved by:	re (kensmith)
2007-07-24 01:24:03 +00:00