4 Commits

Author	SHA1	Message	Date
Ruslan Bukin	98f50c44e3	Update RISC-V port to Privileged Architecture Version 1.9. ... Sponsored by: DARPA, AFRL Sponsored by: HEIF5	2016-08-02 14:50:14 +00:00
Ruslan Bukin	00106e52c2	Add the non-standard "IO interrupt" vector used by lowRISC. ... For now they provide UART irq only. Sponsored by: DARPA, AFRL Sponsored by: HEIF5	2016-04-26 12:56:44 +00:00
Ruslan Bukin	17696c12f5	Add support for symmetric multiprocessing (SMP). ... Tested on Spike simulator with 2 and 16 cores (tlb enabled), so set MAXCPU to 16 at this time. This uses FDT data to get information about CPUs (code based on arm64 mp_machdep). Invalidate entire TLB cache as it is the only way yet. Sponsored by: DARPA, AFRL Sponsored by: HEIF5	2016-02-24 16:50:34 +00:00
Ruslan Bukin	8d7e7a98db	Import RISC-V machine headers. This is a minimal set required to compile ... kernel and userland. Reviewed by: andrew, imp, kib Sponsored by: DARPA, AFRL Sponsored by: HEIF5 Differential Revision: https://reviews.freebsd.org/D4554	2015-12-17 18:44:30 +00:00