and start teaching subsystems about it.
The Atheros MIPS platforms don't guarantee any kind of FIFO consistency
with interrupts in hardware. So software needs to do a flush when it
receives an interrupt and before it calls the interrupt handler.
There are new ones for the QCA934x and QCA955x, so do a few things:
* Get rid of the individual ones (for ethernet and IP2);
* Create a mux and enum listing all the variations on DDR flushes;
* replace the uses of IP2 with the relevant one (which will typically
be "PCI" here);
* call the USB DDR flush before calling the real USB interrupt handlers;
* call the ethernet one upon receiving an interrupt that's for us,
rather than never calling it during operation.
Tested:
* QCA9558 (TP-Link archer c7 v2)
* AR9331 (Carambola 2)
TODO:
* PCI, USB, ethernet, etc need to do a double-check to see if the
interrupt was truely for them before doing the DDR. For now I
prefer "correct" over "fast".
The AR934x and later (which will turn up eventually) have a new GPIO
output configuration option - a real MUX rather than a "GPIO or this
function."
For now I'm squirreling it away in the CPU code just so it's done -
I may move this to the GPIO layer later.
Specifically, this is required for setting up some boards that have
external receive side LNA (low noise amplifier) that gets switched on/off
by the on-chip wireless MAC. If we don't add this support for those
boards then we'll end up with really poor performance.
(I don't yet have one of those APs, but it'll likely show up in a week.)
Obtained from: Linux OpenWRT
* Add the MDIO clock probe during clock initialisation;
* Update the ethernet PLL configuration function to use the correct
values;
* Add a GMAC block configuration to pull the configuration out of hints;
* Add an ethernet switch reconfiguration method.
Tested:
* AR9344 SoC (DB120)
.. however, this has been tested with extra patches in my tree (to fix
the ethernet/MDIO support, SPI support, ethernet switch support)
and thus it isn't enough to bring the full board support up.
This code reads the PLL configuration registers and correctly programs
things so the UART and such can come up.
There's MIPS74k platform issues that need fixing; but this at least brings
things up enough to echo stuff out the serial port and allow for interactive
debugging with ddb.
Tested:
* AR71xx SoCs
* AR933x SoC
* AR9344 board (DB120)
Obtained from: Qualcomm Atheros; Linux/OpenWRT
