0019917542
cache after a data access error we must discard all cache lines. When disabled existing cache lines are not invalidated by stores to memory, so we risk reading stale data that was cached before the data access error if we don't flush them. This is especially fatal when the memory involved is the active part of the kernel or user stack. For good measure we also flush the instruction cache. This fixes random crashes when the X server probes the PCI bus through /dev/pci.
127 lines
4.2 KiB
C
127 lines
4.2 KiB
C
/*
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* Copyright (c) 1996
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* The President and Fellows of Harvard College. All rights reserved.
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* Copyright (c) 1992, 1993
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* The Regents of the University of California. All rights reserved.
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*
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* This software was developed by the Computer Systems Engineering group
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* at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
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* contributed to Berkeley.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Aaron Brown and
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* Harvard University.
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)cache.h 8.1 (Berkeley) 6/11/93
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* from: NetBSD: cache.h,v 1.3 2000/08/01 00:28:02 eeh Exp
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CACHE_H_
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#define _MACHINE_CACHE_H_
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#include <dev/ofw/openfirm.h>
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#define DCACHE_COLOR_BITS (1)
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#define DCACHE_COLORS (1 << DCACHE_COLOR_BITS)
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#define DCACHE_COLOR_MASK (DCACHE_COLORS - 1)
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#define DCACHE_COLOR(va) (((va) >> PAGE_SHIFT) & DCACHE_COLOR_MASK)
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#define DCACHE_OTHER_COLOR(color) \
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((color) ^ DCACHE_COLOR_BITS)
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#define DC_TAG_SHIFT 2
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#define DC_VALID_SHIFT 0
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#define DC_TAG_BITS 28
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#define DC_VALID_BITS 2
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#define DC_TAG_MASK ((1 << DC_TAG_BITS) - 1)
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#define DC_VALID_MASK ((1 << DC_VALID_BITS) - 1)
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#define IC_TAG_SHIFT 7
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#define IC_VALID_SHIFT 36
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#define IC_TAG_BITS 28
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#define IC_VALID_BITS 1
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#define IC_TAG_MASK ((1 << IC_TAG_BITS) - 1)
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#define IC_VALID_MASK ((1 << IC_VALID_BITS) - 1)
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/*
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* Cache control information.
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*/
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struct cacheinfo {
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u_int c_enabled; /* true => cache is enabled */
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u_int ic_size; /* instruction cache */
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u_int ic_set;
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u_int ic_l2set;
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u_int ic_assoc;
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u_int ic_linesize;
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u_int dc_size; /* data cache */
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u_int dc_l2size;
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u_int dc_assoc;
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u_int dc_linesize;
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u_int ec_size; /* external cache info */
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u_int ec_assoc;
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u_int ec_l2set;
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u_int ec_linesize;
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u_int ec_l2linesize;
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};
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#ifdef _KERNEL
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typedef void cache_enable_t(void);
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typedef void cache_flush_t(void);
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typedef void dcache_page_inval_t(vm_paddr_t pa);
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typedef void icache_page_inval_t(vm_paddr_t pa);
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void cache_init(phandle_t node);
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cache_enable_t cheetah_cache_enable;
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cache_flush_t cheetah_cache_flush;
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dcache_page_inval_t cheetah_dcache_page_inval;
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icache_page_inval_t cheetah_icache_page_inval;
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cache_enable_t spitfire_cache_enable;
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cache_flush_t spitfire_cache_flush;
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dcache_page_inval_t spitfire_dcache_page_inval;
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icache_page_inval_t spitfire_icache_page_inval;
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extern cache_enable_t *cache_enable;
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extern cache_flush_t *cache_flush;
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extern dcache_page_inval_t *dcache_page_inval;
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extern icache_page_inval_t *icache_page_inval;
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extern struct cacheinfo cache;
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#endif
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#endif /* !_MACHINE_CACHE_H_ */
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