5e7d0e6482
I'm trying to debug the RX DMA path and help the ath9k guys with "RX dma abort stuck" issue that both our drivers have.
303 lines
8.1 KiB
C
303 lines
8.1 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2008 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ar5212/ar5212.h"
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#include "ar5212/ar5212reg.h"
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#include "ar5212/ar5212desc.h"
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/*
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* Get the RXDP.
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*/
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uint32_t
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ar5212GetRxDP(struct ath_hal *ath)
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{
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return OS_REG_READ(ath, AR_RXDP);
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}
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/*
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* Set the RxDP.
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*/
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void
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ar5212SetRxDP(struct ath_hal *ah, uint32_t rxdp)
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{
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OS_REG_WRITE(ah, AR_RXDP, rxdp);
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HALASSERT(OS_REG_READ(ah, AR_RXDP) == rxdp);
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}
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/*
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* Set Receive Enable bits.
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*/
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void
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ar5212EnableReceive(struct ath_hal *ah)
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{
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
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}
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/*
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* Stop Receive at the DMA engine
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*/
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HAL_BOOL
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ar5212StopDmaReceive(struct ath_hal *ah)
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{
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP);
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
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if (!ath_hal_wait(ah, AR_CR, AR_CR_RXE, 0)) {
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_DMA_STOP_ERR);
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#ifdef AH_DEBUG
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ath_hal_printf(ah, "%s: dma failed to stop in 10ms\n"
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"AR_CR=0x%08x\nAR_DIAG_SW=0x%08x\n",
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__func__,
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OS_REG_READ(ah, AR_CR),
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OS_REG_READ(ah, AR_DIAG_SW));
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#endif
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return AH_FALSE;
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} else {
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return AH_TRUE;
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}
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}
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/*
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* Start Transmit at the PCU engine (unpause receive)
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*/
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void
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ar5212StartPcuReceive(struct ath_hal *ah)
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{
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struct ath_hal_private *ahp = AH_PRIVATE(ah);
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_START);
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OS_REG_WRITE(ah, AR_DIAG_SW,
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OS_REG_READ(ah, AR_DIAG_SW) &~ AR_DIAG_RX_DIS);
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ar5212EnableMibCounters(ah);
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/* NB: restore current settings */
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ar5212AniReset(ah, ahp->ah_curchan, ahp->ah_opmode, AH_TRUE);
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}
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/*
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* Stop Transmit at the PCU engine (pause receive)
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*/
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void
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ar5212StopPcuReceive(struct ath_hal *ah)
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{
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OS_MARK(ah, AH_MARK_RX_CTL, AH_MARK_RX_CTL_PCU_STOP);
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OS_REG_WRITE(ah, AR_DIAG_SW,
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OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_RX_DIS);
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ar5212DisableMibCounters(ah);
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}
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/*
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* Set multicast filter 0 (lower 32-bits)
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* filter 1 (upper 32-bits)
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*/
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void
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ar5212SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
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{
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OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
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}
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/*
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* Clear multicast filter by index
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*/
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HAL_BOOL
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ar5212ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
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{
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uint32_t val;
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if (ix >= 64)
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return AH_FALSE;
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if (ix >= 32) {
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val = OS_REG_READ(ah, AR_MCAST_FIL1);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
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} else {
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val = OS_REG_READ(ah, AR_MCAST_FIL0);
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OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
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}
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return AH_TRUE;
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}
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/*
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* Set multicast filter by index
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*/
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HAL_BOOL
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ar5212SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
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{
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uint32_t val;
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if (ix >= 64)
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return AH_FALSE;
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if (ix >= 32) {
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val = OS_REG_READ(ah, AR_MCAST_FIL1);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
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} else {
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val = OS_REG_READ(ah, AR_MCAST_FIL0);
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OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
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}
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return AH_TRUE;
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}
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/*
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* Get the receive filter.
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*/
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uint32_t
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ar5212GetRxFilter(struct ath_hal *ah)
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{
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uint32_t bits = OS_REG_READ(ah, AR_RX_FILTER);
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uint32_t phybits = OS_REG_READ(ah, AR_PHY_ERR);
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if (phybits & AR_PHY_ERR_RADAR)
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bits |= HAL_RX_FILTER_PHYRADAR;
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if (phybits & (AR_PHY_ERR_OFDM_TIMING|AR_PHY_ERR_CCK_TIMING))
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bits |= HAL_RX_FILTER_PHYERR;
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if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport &&
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(AH5212(ah)->ah_miscMode & AR_MISC_MODE_BSSID_MATCH_FORCE))
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bits |= HAL_RX_FILTER_BSSID;
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return bits;
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}
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/*
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* Set the receive filter.
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*/
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void
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ar5212SetRxFilter(struct ath_hal *ah, uint32_t bits)
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{
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struct ath_hal_5212 *ahp = AH5212(ah);
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uint32_t phybits;
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OS_REG_WRITE(ah, AR_RX_FILTER,
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bits &~ (HAL_RX_FILTER_PHYRADAR|HAL_RX_FILTER_PHYERR|
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HAL_RX_FILTER_BSSID));
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phybits = 0;
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if (bits & HAL_RX_FILTER_PHYRADAR)
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phybits |= AR_PHY_ERR_RADAR;
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if (bits & HAL_RX_FILTER_PHYERR)
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phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
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OS_REG_WRITE(ah, AR_PHY_ERR, phybits);
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if (phybits) {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) | AR_RXCFG_ZLFDMA);
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} else {
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OS_REG_WRITE(ah, AR_RXCFG,
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OS_REG_READ(ah, AR_RXCFG) &~ AR_RXCFG_ZLFDMA);
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}
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if (AH_PRIVATE(ah)->ah_caps.halBssidMatchSupport) {
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if (bits & HAL_RX_FILTER_BSSID)
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ahp->ah_miscMode |= AR_MISC_MODE_BSSID_MATCH_FORCE;
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else
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ahp->ah_miscMode &= ~AR_MISC_MODE_BSSID_MATCH_FORCE;
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OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
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}
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}
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/*
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* Initialize RX descriptor, by clearing the status and setting
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* the size (and any other flags).
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*/
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HAL_BOOL
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ar5212SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t size, u_int flags)
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{
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struct ar5212_desc *ads = AR5212DESC(ds);
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HALASSERT((size &~ AR_BufLen) == 0);
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = size & AR_BufLen;
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if (flags & HAL_RXDESC_INTREQ)
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ads->ds_ctl1 |= AR_RxInterReq;
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ads->ds_rxstatus0 = ads->ds_rxstatus1 = 0;
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return AH_TRUE;
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}
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/*
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* Process an RX descriptor, and return the status to the caller.
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* Copy some hardware specific items into the software portion
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* of the descriptor.
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*
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* NB: the caller is responsible for validating the memory contents
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* of the descriptor (e.g. flushing any cached copy).
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*/
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HAL_STATUS
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ar5212ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t pa, struct ath_desc *nds, uint64_t tsf,
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struct ath_rx_status *rs)
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{
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struct ar5212_desc *ads = AR5212DESC(ds);
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struct ar5212_desc *ands = AR5212DESC(nds);
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if ((ads->ds_rxstatus1 & AR_Done) == 0)
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return HAL_EINPROGRESS;
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/*
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* Given the use of a self-linked tail be very sure that the hw is
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* done with this descriptor; the hw may have done this descriptor
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* once and picked it up again...make sure the hw has moved on.
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*/
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if ((ands->ds_rxstatus1&AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
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return HAL_EINPROGRESS;
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rs->rs_datalen = ads->ds_rxstatus0 & AR_DataLen;
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rs->rs_tstamp = MS(ads->ds_rxstatus1, AR_RcvTimestamp);
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rs->rs_status = 0;
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/* XXX what about KeyCacheMiss? */
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rs->rs_rssi = MS(ads->ds_rxstatus0, AR_RcvSigStrength);
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/* discard invalid h/w rssi data */
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if (rs->rs_rssi == -128)
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rs->rs_rssi = 0;
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if (ads->ds_rxstatus1 & AR_KeyIdxValid)
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rs->rs_keyix = MS(ads->ds_rxstatus1, AR_KeyIdx);
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else
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rs->rs_keyix = HAL_RXKEYIX_INVALID;
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/* NB: caller expected to do rate table mapping */
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rs->rs_rate = MS(ads->ds_rxstatus0, AR_RcvRate);
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rs->rs_antenna = MS(ads->ds_rxstatus0, AR_RcvAntenna);
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rs->rs_more = (ads->ds_rxstatus0 & AR_More) ? 1 : 0;
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if ((ads->ds_rxstatus1 & AR_FrmRcvOK) == 0) {
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/*
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* These four bits should not be set together. The
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* 5212 spec states a Michael error can only occur if
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* DecryptCRCErr not set (and TKIP is used). Experience
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* indicates however that you can also get Michael errors
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* when a CRC error is detected, but these are specious.
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* Consequently we filter them out here so we don't
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* confuse and/or complicate drivers.
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*/
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if (ads->ds_rxstatus1 & AR_CRCErr)
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rs->rs_status |= HAL_RXERR_CRC;
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else if (ads->ds_rxstatus1 & AR_PHYErr) {
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u_int phyerr;
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rs->rs_status |= HAL_RXERR_PHY;
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phyerr = MS(ads->ds_rxstatus1, AR_PHYErrCode);
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rs->rs_phyerr = phyerr;
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if (!AH5212(ah)->ah_hasHwPhyCounters &&
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phyerr != HAL_PHYERR_RADAR)
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ar5212AniPhyErrReport(ah, rs);
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} else if (ads->ds_rxstatus1 & AR_DecryptCRCErr)
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rs->rs_status |= HAL_RXERR_DECRYPT;
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else if (ads->ds_rxstatus1 & AR_MichaelErr)
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rs->rs_status |= HAL_RXERR_MIC;
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}
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return HAL_OK;
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}
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