1373 lines
36 KiB
C
1373 lines
36 KiB
C
/*
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* Copyright (c) 1992 Terrence R. Lambert.
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* Copyright (c) 1982, 1987, 1990 The Regents of the University of California.
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* Copyright (c) 1997 KATO Takenori.
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* Copyright (c) 2001 Tamotsu Hattori.
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* Copyright (c) 2001 Mitsuru IWASAKI.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: Id: machdep.c,v 1.193 1996/06/18 01:22:04 bde Exp
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* $FreeBSD$
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/power.h>
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#include <machine/asmacros.h>
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#include <machine/clock.h>
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#include <machine/cputypes.h>
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#include <machine/segments.h>
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#include <machine/specialreg.h>
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#include <machine/md_var.h>
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#include <i386/isa/icu.h>
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#include <i386/isa/intr_machdep.h>
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#define IDENTBLUE_CYRIX486 0
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#define IDENTBLUE_IBMCPU 1
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#define IDENTBLUE_CYRIXM2 2
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/* XXX - should be in header file: */
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void printcpuinfo(void);
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void finishidentcpu(void);
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void earlysetcpuclass(void);
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#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
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void enable_K5_wt_alloc(void);
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void enable_K6_wt_alloc(void);
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void enable_K6_2_wt_alloc(void);
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#endif
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void panicifcpuunsupported(void);
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static void identifycyrix(void);
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#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
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static void print_AMD_features(u_int *regs);
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#endif
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static void print_AMD_info(u_int amd_maxregs);
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static void print_AMD_assoc(int i);
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static void print_transmeta_info(void);
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static void setup_tmx86_longrun(void);
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u_int cyrix_did; /* Device ID of Cyrix CPU */
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int cpu_class = CPUCLASS_386; /* least common denominator */
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char machine[] = "i386";
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SYSCTL_STRING(_hw, HW_MACHINE, machine, CTLFLAG_RD,
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machine, 0, "Machine class");
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static char cpu_model[128];
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SYSCTL_STRING(_hw, HW_MODEL, model, CTLFLAG_RD,
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cpu_model, 0, "Machine model");
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static struct cpu_nameclass i386_cpus[] = {
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{ "Intel 80286", CPUCLASS_286 }, /* CPU_286 */
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{ "i386SX", CPUCLASS_386 }, /* CPU_386SX */
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{ "i386DX", CPUCLASS_386 }, /* CPU_386 */
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{ "i486SX", CPUCLASS_486 }, /* CPU_486SX */
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{ "i486DX", CPUCLASS_486 }, /* CPU_486 */
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{ "Pentium", CPUCLASS_586 }, /* CPU_586 */
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{ "Cyrix 486", CPUCLASS_486 }, /* CPU_486DLC */
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{ "Pentium Pro", CPUCLASS_686 }, /* CPU_686 */
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{ "Cyrix 5x86", CPUCLASS_486 }, /* CPU_M1SC */
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{ "Cyrix 6x86", CPUCLASS_486 }, /* CPU_M1 */
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{ "Blue Lightning", CPUCLASS_486 }, /* CPU_BLUE */
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{ "Cyrix 6x86MX", CPUCLASS_686 }, /* CPU_M2 */
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{ "NexGen 586", CPUCLASS_386 }, /* CPU_NX586 (XXX) */
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{ "Cyrix 486S/DX", CPUCLASS_486 }, /* CPU_CY486DX */
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{ "Pentium II", CPUCLASS_686 }, /* CPU_PII */
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{ "Pentium III", CPUCLASS_686 }, /* CPU_PIII */
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{ "Pentium 4", CPUCLASS_686 }, /* CPU_P4 */
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};
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#if defined(I586_CPU) && !defined(NO_F00F_HACK)
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int has_f00f_bug = 0; /* Initialized so that it can be patched. */
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#endif
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void
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printcpuinfo(void)
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{
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#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
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u_int regs[4];
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#endif
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u_int nreg = 0;
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cpu_class = i386_cpus[cpu].cpu_class;
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printf("CPU: ");
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strncpy(cpu_model, i386_cpus[cpu].cpu_name, sizeof cpu_model);
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#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
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if (strcmp(cpu_vendor,"GenuineIntel") == 0) {
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if ((cpu_id & 0xf00) > 0x300) {
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cpu_model[0] = '\0';
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switch (cpu_id & 0x3000) {
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case 0x1000:
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strcpy(cpu_model, "Overdrive ");
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break;
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case 0x2000:
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strcpy(cpu_model, "Dual ");
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break;
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}
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switch (cpu_id & 0xf00) {
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case 0x400:
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strcat(cpu_model, "i486 ");
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/* Check the particular flavor of 486 */
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switch (cpu_id & 0xf0) {
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case 0x00:
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case 0x10:
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strcat(cpu_model, "DX");
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break;
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case 0x20:
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strcat(cpu_model, "SX");
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break;
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case 0x30:
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strcat(cpu_model, "DX2");
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break;
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case 0x40:
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strcat(cpu_model, "SL");
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break;
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case 0x50:
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strcat(cpu_model, "SX2");
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break;
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case 0x70:
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strcat(cpu_model,
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"DX2 Write-Back Enhanced");
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break;
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case 0x80:
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strcat(cpu_model, "DX4");
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break;
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}
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break;
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case 0x500:
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/* Check the particular flavor of 586 */
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strcat(cpu_model, "Pentium");
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switch (cpu_id & 0xf0) {
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case 0x00:
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strcat(cpu_model, " A-step");
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break;
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case 0x10:
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strcat(cpu_model, "/P5");
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break;
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case 0x20:
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strcat(cpu_model, "/P54C");
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break;
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case 0x30:
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strcat(cpu_model, "/P54T Overdrive");
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break;
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case 0x40:
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strcat(cpu_model, "/P55C");
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break;
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case 0x70:
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strcat(cpu_model, "/P54C");
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break;
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case 0x80:
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strcat(cpu_model, "/P55C (quarter-micron)");
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break;
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default:
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/* nothing */
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break;
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}
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#if defined(I586_CPU) && !defined(NO_F00F_HACK)
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/*
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* XXX - If/when Intel fixes the bug, this
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* should also check the version of the
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* CPU, not just that it's a Pentium.
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*/
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has_f00f_bug = 1;
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#endif
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break;
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case 0x600:
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/* Check the particular flavor of 686 */
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switch (cpu_id & 0xf0) {
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case 0x00:
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strcat(cpu_model, "Pentium Pro A-step");
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break;
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case 0x10:
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strcat(cpu_model, "Pentium Pro");
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break;
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case 0x30:
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case 0x50:
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case 0x60:
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strcat(cpu_model,
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"Pentium II/Pentium II Xeon/Celeron");
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cpu = CPU_PII;
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break;
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case 0x70:
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case 0x80:
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case 0xa0:
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case 0xb0:
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strcat(cpu_model,
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"Pentium III/Pentium III Xeon/Celeron");
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cpu = CPU_PIII;
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break;
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default:
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strcat(cpu_model, "Unknown 80686");
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break;
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}
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break;
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case 0xf00:
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strcat(cpu_model, "Pentium 4");
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cpu = CPU_P4;
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break;
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default:
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strcat(cpu_model, "unknown");
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break;
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}
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}
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} else if (strcmp(cpu_vendor,"AuthenticAMD") == 0) {
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/*
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* Values taken from AMD Processor Recognition
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* http://www.amd.com/K6/k6docs/pdf/20734g.pdf
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* (also describes ``Features'' encodings.
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*/
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strcpy(cpu_model, "AMD ");
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switch (cpu_id & 0xFF0) {
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case 0x410:
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strcat(cpu_model, "Standard Am486DX");
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break;
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case 0x430:
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strcat(cpu_model, "Enhanced Am486DX2 Write-Through");
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break;
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case 0x470:
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strcat(cpu_model, "Enhanced Am486DX2 Write-Back");
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break;
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case 0x480:
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strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Through");
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break;
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case 0x490:
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strcat(cpu_model, "Enhanced Am486DX4/Am5x86 Write-Back");
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break;
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case 0x4E0:
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strcat(cpu_model, "Am5x86 Write-Through");
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break;
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case 0x4F0:
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strcat(cpu_model, "Am5x86 Write-Back");
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break;
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case 0x500:
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strcat(cpu_model, "K5 model 0");
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tsc_is_broken = 1;
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break;
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case 0x510:
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strcat(cpu_model, "K5 model 1");
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break;
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case 0x520:
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strcat(cpu_model, "K5 PR166 (model 2)");
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break;
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case 0x530:
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strcat(cpu_model, "K5 PR200 (model 3)");
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break;
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case 0x560:
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strcat(cpu_model, "K6");
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break;
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case 0x570:
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strcat(cpu_model, "K6 266 (model 1)");
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break;
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case 0x580:
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strcat(cpu_model, "K6-2");
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break;
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case 0x590:
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strcat(cpu_model, "K6-III");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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}
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#if defined(I586_CPU) && defined(CPU_WT_ALLOC)
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if ((cpu_id & 0xf00) == 0x500) {
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if (((cpu_id & 0x0f0) > 0)
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&& ((cpu_id & 0x0f0) < 0x60)
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&& ((cpu_id & 0x00f) > 3))
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enable_K5_wt_alloc();
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else if (((cpu_id & 0x0f0) > 0x80)
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|| (((cpu_id & 0x0f0) == 0x80)
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&& (cpu_id & 0x00f) > 0x07))
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enable_K6_2_wt_alloc();
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else if ((cpu_id & 0x0f0) > 0x50)
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enable_K6_wt_alloc();
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}
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#endif
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do_cpuid(0x80000000, regs);
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nreg = regs[0];
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if (nreg >= 0x80000004) {
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do_cpuid(0x80000002, regs);
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memcpy(cpu_model, regs, sizeof regs);
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do_cpuid(0x80000003, regs);
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memcpy(cpu_model+16, regs, sizeof regs);
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do_cpuid(0x80000004, regs);
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memcpy(cpu_model+32, regs, sizeof regs);
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}
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} else if (strcmp(cpu_vendor,"CyrixInstead") == 0) {
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strcpy(cpu_model, "Cyrix ");
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switch (cpu_id & 0xff0) {
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case 0x440:
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strcat(cpu_model, "MediaGX");
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break;
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case 0x520:
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strcat(cpu_model, "6x86");
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break;
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case 0x540:
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cpu_class = CPUCLASS_586;
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strcat(cpu_model, "GXm");
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break;
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case 0x600:
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strcat(cpu_model, "6x86MX");
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break;
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default:
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/*
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* Even though CPU supports the cpuid
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* instruction, it can be disabled.
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* Therefore, this routine supports all Cyrix
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* CPUs.
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*/
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switch (cyrix_did & 0xf0) {
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case 0x00:
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switch (cyrix_did & 0x0f) {
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case 0x00:
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strcat(cpu_model, "486SLC");
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break;
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case 0x01:
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strcat(cpu_model, "486DLC");
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break;
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case 0x02:
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strcat(cpu_model, "486SLC2");
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break;
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case 0x03:
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strcat(cpu_model, "486DLC2");
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break;
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case 0x04:
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strcat(cpu_model, "486SRx");
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break;
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case 0x05:
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strcat(cpu_model, "486DRx");
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break;
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case 0x06:
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strcat(cpu_model, "486SRx2");
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break;
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case 0x07:
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strcat(cpu_model, "486DRx2");
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break;
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case 0x08:
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strcat(cpu_model, "486SRu");
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break;
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case 0x09:
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strcat(cpu_model, "486DRu");
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break;
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case 0x0a:
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strcat(cpu_model, "486SRu2");
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break;
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case 0x0b:
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strcat(cpu_model, "486DRu2");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
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}
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break;
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case 0x10:
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switch (cyrix_did & 0x0f) {
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case 0x00:
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strcat(cpu_model, "486S");
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break;
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case 0x01:
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strcat(cpu_model, "486S2");
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break;
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case 0x02:
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strcat(cpu_model, "486Se");
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break;
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case 0x03:
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strcat(cpu_model, "486S2e");
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break;
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case 0x0a:
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strcat(cpu_model, "486DX");
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break;
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case 0x0b:
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strcat(cpu_model, "486DX2");
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break;
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case 0x0f:
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strcat(cpu_model, "486DX4");
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break;
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default:
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strcat(cpu_model, "Unknown");
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break;
|
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}
|
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break;
|
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case 0x20:
|
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if ((cyrix_did & 0x0f) < 8)
|
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strcat(cpu_model, "6x86"); /* Where did you get it? */
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else
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strcat(cpu_model, "5x86");
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break;
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case 0x30:
|
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strcat(cpu_model, "6x86");
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break;
|
|
case 0x40:
|
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if ((cyrix_did & 0xf000) == 0x3000) {
|
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cpu_class = CPUCLASS_586;
|
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strcat(cpu_model, "GXm");
|
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} else
|
|
strcat(cpu_model, "MediaGX");
|
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break;
|
|
case 0x50:
|
|
strcat(cpu_model, "6x86MX");
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break;
|
|
case 0xf0:
|
|
switch (cyrix_did & 0x0f) {
|
|
case 0x0d:
|
|
strcat(cpu_model, "Overdrive CPU");
|
|
case 0x0e:
|
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strcpy(cpu_model, "Texas Instruments 486SXL");
|
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break;
|
|
case 0x0f:
|
|
strcat(cpu_model, "486SLC/DLC");
|
|
break;
|
|
default:
|
|
strcat(cpu_model, "Unknown");
|
|
break;
|
|
}
|
|
break;
|
|
default:
|
|
strcat(cpu_model, "Unknown");
|
|
break;
|
|
}
|
|
break;
|
|
}
|
|
} else if (strcmp(cpu_vendor, "RiseRiseRise") == 0) {
|
|
strcpy(cpu_model, "Rise ");
|
|
switch (cpu_id & 0xff0) {
|
|
case 0x500:
|
|
strcat(cpu_model, "mP6");
|
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break;
|
|
default:
|
|
strcat(cpu_model, "Unknown");
|
|
}
|
|
} else if (strcmp(cpu_vendor, "CentaurHauls") == 0) {
|
|
switch (cpu_id & 0xff0) {
|
|
case 0x540:
|
|
strcpy(cpu_model, "IDT WinChip C6");
|
|
tsc_is_broken = 1;
|
|
break;
|
|
case 0x580:
|
|
strcpy(cpu_model, "IDT WinChip 2");
|
|
break;
|
|
case 0x670:
|
|
strcpy(cpu_model, "VIA C3 Samuel 2");
|
|
break;
|
|
default:
|
|
strcpy(cpu_model, "VIA/IDT Unknown");
|
|
}
|
|
} else if (strcmp(cpu_vendor, "IBM") == 0) {
|
|
strcpy(cpu_model, "Blue Lightning CPU");
|
|
} else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
|
|
strcmp(cpu_vendor, "TransmetaCPU") == 0) {
|
|
do_cpuid(0x80000000, regs);
|
|
nreg = regs[0];
|
|
if (nreg >= 0x80000004) {
|
|
do_cpuid(0x80000002, regs);
|
|
memcpy(cpu_model, regs, sizeof regs);
|
|
do_cpuid(0x80000003, regs);
|
|
memcpy(cpu_model+16, regs, sizeof regs);
|
|
do_cpuid(0x80000004, regs);
|
|
memcpy(cpu_model+32, regs, sizeof regs);
|
|
}
|
|
cpu_model[64] = '\0';
|
|
}
|
|
#endif
|
|
|
|
printf("%s (", cpu_model);
|
|
switch(cpu_class) {
|
|
case CPUCLASS_286:
|
|
printf("286");
|
|
break;
|
|
#if defined(I386_CPU)
|
|
case CPUCLASS_386:
|
|
printf("386");
|
|
break;
|
|
#endif
|
|
#if defined(I486_CPU)
|
|
case CPUCLASS_486:
|
|
printf("486");
|
|
bzero = i486_bzero;
|
|
break;
|
|
#endif
|
|
#if defined(I586_CPU)
|
|
case CPUCLASS_586:
|
|
printf("%d.%02d-MHz ",
|
|
(tsc_freq + 4999) / 1000000,
|
|
((tsc_freq + 4999) / 10000) % 100);
|
|
printf("586");
|
|
break;
|
|
#endif
|
|
#if defined(I686_CPU)
|
|
case CPUCLASS_686:
|
|
printf("%d.%02d-MHz ",
|
|
(tsc_freq + 4999) / 1000000,
|
|
((tsc_freq + 4999) / 10000) % 100);
|
|
printf("686");
|
|
break;
|
|
#endif
|
|
default:
|
|
printf("Unknown"); /* will panic below... */
|
|
}
|
|
printf("-class CPU)\n");
|
|
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
|
|
if(*cpu_vendor)
|
|
printf(" Origin = \"%s\"",cpu_vendor);
|
|
if(cpu_id)
|
|
printf(" Id = 0x%x", cpu_id);
|
|
|
|
if (strcmp(cpu_vendor, "GenuineIntel") == 0 ||
|
|
strcmp(cpu_vendor, "AuthenticAMD") == 0 ||
|
|
strcmp(cpu_vendor, "RiseRiseRise") == 0 ||
|
|
strcmp(cpu_vendor, "CentaurHauls") == 0 ||
|
|
((strcmp(cpu_vendor, "CyrixInstead") == 0) &&
|
|
((cpu_id & 0xf00) > 0x500))) {
|
|
printf(" Stepping = %u", cpu_id & 0xf);
|
|
if (strcmp(cpu_vendor, "CyrixInstead") == 0)
|
|
printf(" DIR=0x%04x", cyrix_did);
|
|
if (cpu_high > 0) {
|
|
/*
|
|
* Here we should probably set up flags indicating
|
|
* whether or not various features are available.
|
|
* The interesting ones are probably VME, PSE, PAE,
|
|
* and PGE. The code already assumes without bothering
|
|
* to check that all CPUs >= Pentium have a TSC and
|
|
* MSRs.
|
|
*/
|
|
printf("\n Features=0x%b", cpu_feature,
|
|
"\020"
|
|
"\001FPU" /* Integral FPU */
|
|
"\002VME" /* Extended VM86 mode support */
|
|
"\003DE" /* Debugging Extensions (CR4.DE) */
|
|
"\004PSE" /* 4MByte page tables */
|
|
"\005TSC" /* Timestamp counter */
|
|
"\006MSR" /* Machine specific registers */
|
|
"\007PAE" /* Physical address extension */
|
|
"\010MCE" /* Machine Check support */
|
|
"\011CX8" /* CMPEXCH8 instruction */
|
|
"\012APIC" /* SMP local APIC */
|
|
"\013oldMTRR" /* Previous implementation of MTRR */
|
|
"\014SEP" /* Fast System Call */
|
|
"\015MTRR" /* Memory Type Range Registers */
|
|
"\016PGE" /* PG_G (global bit) support */
|
|
"\017MCA" /* Machine Check Architecture */
|
|
"\020CMOV" /* CMOV instruction */
|
|
"\021PAT" /* Page attributes table */
|
|
"\022PSE36" /* 36 bit address space support */
|
|
"\023PN" /* Processor Serial number */
|
|
"\024CLFLUSH" /* Has the CLFLUSH instruction */
|
|
"\025<b20>"
|
|
"\026DTS" /* Debug Trace Store */
|
|
"\027ACPI" /* ACPI support */
|
|
"\030MMX" /* MMX instructions */
|
|
"\031FXSR" /* FXSAVE/FXRSTOR */
|
|
"\032SSE" /* Streaming SIMD Extensions */
|
|
"\033SSE2" /* Streaming SIMD Extensions #2 */
|
|
"\034SS" /* Self snoop */
|
|
"\035HTT" /* Hyperthreading (see EBX bit 16-23) */
|
|
"\036TM" /* Thermal Monitor clock slowdown */
|
|
"\037IA64" /* CPU can execute IA64 instructions */
|
|
"\040<b31>"
|
|
);
|
|
}
|
|
if (strcmp(cpu_vendor, "AuthenticAMD") == 0 &&
|
|
nreg >= 0x80000001)
|
|
print_AMD_features(regs);
|
|
} else if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
|
|
printf(" DIR=0x%04x", cyrix_did);
|
|
printf(" Stepping=%u", (cyrix_did & 0xf000) >> 12);
|
|
printf(" Revision=%u", (cyrix_did & 0x0f00) >> 8);
|
|
#ifndef CYRIX_CACHE_REALLY_WORKS
|
|
if (cpu == CPU_M1 && (cyrix_did & 0xff00) < 0x1700)
|
|
printf("\n CPU cache: write-through mode");
|
|
#endif
|
|
}
|
|
/* Avoid ugly blank lines: only print newline when we have to. */
|
|
if (*cpu_vendor || cpu_id)
|
|
printf("\n");
|
|
|
|
#endif
|
|
if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
|
|
strcmp(cpu_vendor, "TransmetaCPU") == 0) {
|
|
setup_tmx86_longrun();
|
|
}
|
|
|
|
if (!bootverbose)
|
|
return;
|
|
|
|
if (strcmp(cpu_vendor, "AuthenticAMD") == 0)
|
|
print_AMD_info(nreg);
|
|
else if (strcmp(cpu_vendor, "GenuineTMx86") == 0 ||
|
|
strcmp(cpu_vendor, "TransmetaCPU") == 0)
|
|
print_transmeta_info();
|
|
|
|
#ifdef I686_CPU
|
|
/*
|
|
* XXX - Do PPro CPUID level=2 stuff here?
|
|
*
|
|
* No, but maybe in a print_Intel_info() function called from here.
|
|
*/
|
|
#endif
|
|
}
|
|
|
|
void
|
|
panicifcpuunsupported(void)
|
|
{
|
|
|
|
#if !defined(I386_CPU) && !defined(I486_CPU) && !defined(I586_CPU) && !defined(I686_CPU)
|
|
#error This kernel is not configured for one of the supported CPUs
|
|
#endif
|
|
#if defined(I386_CPU) && (defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU))
|
|
#error I386_CPU is mutually exclusive with the other cpu types.
|
|
#endif
|
|
/*
|
|
* Now that we have told the user what they have,
|
|
* let them know if that machine type isn't configured.
|
|
*/
|
|
switch (cpu_class) {
|
|
case CPUCLASS_286: /* a 286 should not make it this far, anyway */
|
|
#if !defined(I386_CPU)
|
|
case CPUCLASS_386:
|
|
#endif
|
|
#if !defined(I486_CPU)
|
|
case CPUCLASS_486:
|
|
#endif
|
|
#if !defined(I586_CPU)
|
|
case CPUCLASS_586:
|
|
#endif
|
|
#if !defined(I686_CPU)
|
|
case CPUCLASS_686:
|
|
#endif
|
|
panic("CPU class not configured");
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
static volatile u_int trap_by_rdmsr;
|
|
|
|
/*
|
|
* Special exception 6 handler.
|
|
* The rdmsr instruction generates invalid opcodes fault on 486-class
|
|
* Cyrix CPU. Stacked eip register points the rdmsr instruction in the
|
|
* function identblue() when this handler is called. Stacked eip should
|
|
* be advanced.
|
|
*/
|
|
inthand_t bluetrap6;
|
|
__asm
|
|
(" \
|
|
.text; \
|
|
.p2align 2,0x90; \
|
|
.type " __XSTRING(CNAME(bluetrap6)) ",@function; \
|
|
" __XSTRING(CNAME(bluetrap6)) ": \
|
|
ss; \
|
|
movl $0xa8c1d," __XSTRING(CNAME(trap_by_rdmsr)) "; \
|
|
addl $2, (%esp); /* rdmsr is a 2-byte instruction */ \
|
|
iret \
|
|
");
|
|
|
|
/*
|
|
* Special exception 13 handler.
|
|
* Accessing non-existent MSR generates general protection fault.
|
|
*/
|
|
inthand_t bluetrap13;
|
|
__asm
|
|
(" \
|
|
.text; \
|
|
.p2align 2,0x90; \
|
|
.type " __XSTRING(CNAME(bluetrap13)) ",@function; \
|
|
" __XSTRING(CNAME(bluetrap13)) ": \
|
|
ss; \
|
|
movl $0xa89c4," __XSTRING(CNAME(trap_by_rdmsr)) "; \
|
|
popl %eax; /* discard errorcode. */ \
|
|
addl $2, (%esp); /* rdmsr is a 2-bytes instruction. */ \
|
|
iret; \
|
|
");
|
|
|
|
/*
|
|
* Distinguish IBM Blue Lightning CPU from Cyrix CPUs that does not
|
|
* support cpuid instruction. This function should be called after
|
|
* loading interrupt descriptor table register.
|
|
*
|
|
* I don't like this method that handles fault, but I couldn't get
|
|
* information for any other methods. Does blue giant know?
|
|
*/
|
|
static int
|
|
identblue(void)
|
|
{
|
|
|
|
trap_by_rdmsr = 0;
|
|
|
|
/*
|
|
* Cyrix 486-class CPU does not support rdmsr instruction.
|
|
* The rdmsr instruction generates invalid opcode fault, and exception
|
|
* will be trapped by bluetrap6() on Cyrix 486-class CPU. The
|
|
* bluetrap6() set the magic number to trap_by_rdmsr.
|
|
*/
|
|
setidt(6, bluetrap6, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
|
|
/*
|
|
* Certain BIOS disables cpuid instruction of Cyrix 6x86MX CPU.
|
|
* In this case, rdmsr generates general protection fault, and
|
|
* exception will be trapped by bluetrap13().
|
|
*/
|
|
setidt(13, bluetrap13, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
|
|
|
|
rdmsr(0x1002); /* Cyrix CPU generates fault. */
|
|
|
|
if (trap_by_rdmsr == 0xa8c1d)
|
|
return IDENTBLUE_CYRIX486;
|
|
else if (trap_by_rdmsr == 0xa89c4)
|
|
return IDENTBLUE_CYRIXM2;
|
|
return IDENTBLUE_IBMCPU;
|
|
}
|
|
|
|
|
|
/*
|
|
* identifycyrix() set lower 16 bits of cyrix_did as follows:
|
|
*
|
|
* F E D C B A 9 8 7 6 5 4 3 2 1 0
|
|
* +-------+-------+---------------+
|
|
* | SID | RID | Device ID |
|
|
* | (DIR 1) | (DIR 0) |
|
|
* +-------+-------+---------------+
|
|
*/
|
|
static void
|
|
identifycyrix(void)
|
|
{
|
|
u_int eflags;
|
|
int ccr2_test = 0, dir_test = 0;
|
|
u_char ccr2, ccr3;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
|
|
ccr2 = read_cyrix_reg(CCR2);
|
|
write_cyrix_reg(CCR2, ccr2 ^ CCR2_LOCK_NW);
|
|
read_cyrix_reg(CCR2);
|
|
if (read_cyrix_reg(CCR2) != ccr2)
|
|
ccr2_test = 1;
|
|
write_cyrix_reg(CCR2, ccr2);
|
|
|
|
ccr3 = read_cyrix_reg(CCR3);
|
|
write_cyrix_reg(CCR3, ccr3 ^ CCR3_MAPEN3);
|
|
read_cyrix_reg(CCR3);
|
|
if (read_cyrix_reg(CCR3) != ccr3)
|
|
dir_test = 1; /* CPU supports DIRs. */
|
|
write_cyrix_reg(CCR3, ccr3);
|
|
|
|
if (dir_test) {
|
|
/* Device ID registers are available. */
|
|
cyrix_did = read_cyrix_reg(DIR1) << 8;
|
|
cyrix_did += read_cyrix_reg(DIR0);
|
|
} else if (ccr2_test)
|
|
cyrix_did = 0x0010; /* 486S A-step */
|
|
else
|
|
cyrix_did = 0x00ff; /* Old 486SLC/DLC and TI486SXLC/SXL */
|
|
|
|
write_eflags(eflags);
|
|
}
|
|
|
|
/*
|
|
* Final stage of CPU identification. -- Should I check TI?
|
|
*/
|
|
void
|
|
finishidentcpu(void)
|
|
{
|
|
int isblue = 0;
|
|
u_char ccr3;
|
|
u_int regs[4];
|
|
|
|
if (strcmp(cpu_vendor, "CyrixInstead") == 0) {
|
|
if (cpu == CPU_486) {
|
|
/*
|
|
* These conditions are equivalent to:
|
|
* - CPU does not support cpuid instruction.
|
|
* - Cyrix/IBM CPU is detected.
|
|
*/
|
|
isblue = identblue();
|
|
if (isblue == IDENTBLUE_IBMCPU) {
|
|
strcpy(cpu_vendor, "IBM");
|
|
cpu = CPU_BLUE;
|
|
return;
|
|
}
|
|
}
|
|
switch (cpu_id & 0xf00) {
|
|
case 0x600:
|
|
/*
|
|
* Cyrix's datasheet does not describe DIRs.
|
|
* Therefor, I assume it does not have them
|
|
* and use the result of the cpuid instruction.
|
|
* XXX they seem to have it for now at least. -Peter
|
|
*/
|
|
identifycyrix();
|
|
cpu = CPU_M2;
|
|
break;
|
|
default:
|
|
identifycyrix();
|
|
/*
|
|
* This routine contains a trick.
|
|
* Don't check (cpu_id & 0x00f0) == 0x50 to detect M2, now.
|
|
*/
|
|
switch (cyrix_did & 0x00f0) {
|
|
case 0x00:
|
|
case 0xf0:
|
|
cpu = CPU_486DLC;
|
|
break;
|
|
case 0x10:
|
|
cpu = CPU_CY486DX;
|
|
break;
|
|
case 0x20:
|
|
if ((cyrix_did & 0x000f) < 8)
|
|
cpu = CPU_M1;
|
|
else
|
|
cpu = CPU_M1SC;
|
|
break;
|
|
case 0x30:
|
|
cpu = CPU_M1;
|
|
break;
|
|
case 0x40:
|
|
/* MediaGX CPU */
|
|
cpu = CPU_M1SC;
|
|
break;
|
|
default:
|
|
/* M2 and later CPUs are treated as M2. */
|
|
cpu = CPU_M2;
|
|
|
|
/*
|
|
* enable cpuid instruction.
|
|
*/
|
|
ccr3 = read_cyrix_reg(CCR3);
|
|
write_cyrix_reg(CCR3, CCR3_MAPEN0);
|
|
write_cyrix_reg(CCR4, read_cyrix_reg(CCR4) | CCR4_CPUID);
|
|
write_cyrix_reg(CCR3, ccr3);
|
|
|
|
do_cpuid(0, regs);
|
|
cpu_high = regs[0]; /* eax */
|
|
do_cpuid(1, regs);
|
|
cpu_id = regs[0]; /* eax */
|
|
cpu_feature = regs[3]; /* edx */
|
|
break;
|
|
}
|
|
}
|
|
} else if (cpu == CPU_486 && *cpu_vendor == '\0') {
|
|
/*
|
|
* There are BlueLightning CPUs that do not change
|
|
* undefined flags by dividing 5 by 2. In this case,
|
|
* the CPU identification routine in locore.s leaves
|
|
* cpu_vendor null string and puts CPU_486 into the
|
|
* cpu.
|
|
*/
|
|
isblue = identblue();
|
|
if (isblue == IDENTBLUE_IBMCPU) {
|
|
strcpy(cpu_vendor, "IBM");
|
|
cpu = CPU_BLUE;
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* This routine is called specifically to set up cpu_class before
|
|
* startrtclock() uses it. Probably this should be rearranged so that
|
|
* startrtclock() doesn't need to run until after identifycpu() has been
|
|
* called. Another alternative formulation would be for this routine
|
|
* to do all the identification work, and make identifycpu() into a
|
|
* printing-only routine.
|
|
*/
|
|
void
|
|
earlysetcpuclass(void)
|
|
{
|
|
|
|
cpu_class = i386_cpus[cpu].cpu_class;
|
|
}
|
|
|
|
static void
|
|
print_AMD_assoc(int i)
|
|
{
|
|
if (i == 255)
|
|
printf(", fully associative\n");
|
|
else
|
|
printf(", %d-way associative\n", i);
|
|
}
|
|
|
|
static void
|
|
print_AMD_info(u_int amd_maxregs)
|
|
{
|
|
quad_t amd_whcr;
|
|
|
|
if (amd_maxregs >= 0x80000005) {
|
|
u_int regs[4];
|
|
|
|
do_cpuid(0x80000005, regs);
|
|
printf("Data TLB: %d entries", (regs[1] >> 16) & 0xff);
|
|
print_AMD_assoc(regs[1] >> 24);
|
|
printf("Instruction TLB: %d entries", regs[1] & 0xff);
|
|
print_AMD_assoc((regs[1] >> 8) & 0xff);
|
|
printf("L1 data cache: %d kbytes", regs[2] >> 24);
|
|
printf(", %d bytes/line", regs[2] & 0xff);
|
|
printf(", %d lines/tag", (regs[2] >> 8) & 0xff);
|
|
print_AMD_assoc((regs[2] >> 16) & 0xff);
|
|
printf("L1 instruction cache: %d kbytes", regs[3] >> 24);
|
|
printf(", %d bytes/line", regs[3] & 0xff);
|
|
printf(", %d lines/tag", (regs[3] >> 8) & 0xff);
|
|
print_AMD_assoc((regs[3] >> 16) & 0xff);
|
|
if (amd_maxregs >= 0x80000006) { /* K6-III only */
|
|
do_cpuid(0x80000006, regs);
|
|
printf("L2 internal cache: %d kbytes", regs[2] >> 16);
|
|
printf(", %d bytes/line", regs[2] & 0xff);
|
|
printf(", %d lines/tag", (regs[2] >> 8) & 0x0f);
|
|
print_AMD_assoc((regs[2] >> 12) & 0x0f);
|
|
}
|
|
}
|
|
if (((cpu_id & 0xf00) == 0x500)
|
|
&& (((cpu_id & 0x0f0) > 0x80)
|
|
|| (((cpu_id & 0x0f0) == 0x80)
|
|
&& (cpu_id & 0x00f) > 0x07))) {
|
|
/* K6-2(new core [Stepping 8-F]), K6-III or later */
|
|
amd_whcr = rdmsr(0xc0000082);
|
|
if (!(amd_whcr & (0x3ff << 22))) {
|
|
printf("Write Allocate Disable\n");
|
|
} else {
|
|
printf("Write Allocate Enable Limit: %dM bytes\n",
|
|
(u_int32_t)((amd_whcr & (0x3ff << 22)) >> 22) * 4);
|
|
printf("Write Allocate 15-16M bytes: %s\n",
|
|
(amd_whcr & (1 << 16)) ? "Enable" : "Disable");
|
|
}
|
|
} else if (((cpu_id & 0xf00) == 0x500)
|
|
&& ((cpu_id & 0x0f0) > 0x50)) {
|
|
/* K6, K6-2(old core) */
|
|
amd_whcr = rdmsr(0xc0000082);
|
|
if (!(amd_whcr & (0x7f << 1))) {
|
|
printf("Write Allocate Disable\n");
|
|
} else {
|
|
printf("Write Allocate Enable Limit: %dM bytes\n",
|
|
(u_int32_t)((amd_whcr & (0x7f << 1)) >> 1) * 4);
|
|
printf("Write Allocate 15-16M bytes: %s\n",
|
|
(amd_whcr & 0x0001) ? "Enable" : "Disable");
|
|
printf("Hardware Write Allocate Control: %s\n",
|
|
(amd_whcr & 0x0100) ? "Enable" : "Disable");
|
|
}
|
|
}
|
|
}
|
|
|
|
#if defined(I486_CPU) || defined(I586_CPU) || defined(I686_CPU)
|
|
static void
|
|
print_AMD_features(u_int *regs)
|
|
{
|
|
/*
|
|
* Values taken from AMD Processor Recognition
|
|
* http://www.amd.com/products/cpg/athlon/techdocs/pdf/20734.pdf
|
|
*/
|
|
do_cpuid(0x80000001, regs);
|
|
printf("\n AMD Features=0x%b", regs[3] &~ cpu_feature,
|
|
"\020" /* in hex */
|
|
"\001FPU" /* Integral FPU */
|
|
"\002VME" /* Extended VM86 mode support */
|
|
"\003DE" /* Debug extensions */
|
|
"\004PSE" /* 4MByte page tables */
|
|
"\005TSC" /* Timestamp counter */
|
|
"\006MSR" /* Machine specific registers */
|
|
"\007PAE" /* Physical address extension */
|
|
"\010MCE" /* Machine Check support */
|
|
"\011CX8" /* CMPEXCH8 instruction */
|
|
"\012APIC" /* SMP local APIC */
|
|
"\013<b10>"
|
|
"\014SYSCALL" /* SYSENTER/SYSEXIT instructions */
|
|
"\015MTRR" /* Memory Type Range Registers */
|
|
"\016PGE" /* PG_G (global bit) support */
|
|
"\017MCA" /* Machine Check Architecture */
|
|
"\020ICMOV" /* CMOV instruction */
|
|
"\021PAT" /* Page attributes table */
|
|
"\022PGE36" /* 36 bit address space support */
|
|
"\023RSVD" /* Reserved, unknown */
|
|
"\024MP" /* Multiprocessor Capable */
|
|
"\025<b20>"
|
|
"\026<b21>"
|
|
"\027AMIE" /* AMD MMX Instruction Extensions */
|
|
"\030MMX"
|
|
"\031FXSAVE" /* FXSAVE/FXRSTOR */
|
|
"\032<b25>"
|
|
"\033<b26>"
|
|
"\034<b27>"
|
|
"\035<b28>"
|
|
"\036<b29>"
|
|
"\037DSP" /* AMD 3DNow! Instruction Extensions */
|
|
"\0403DNow!"
|
|
);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Transmeta Crusoe LongRun Support by Tamotsu Hattori.
|
|
*/
|
|
|
|
#define MSR_TMx86_LONGRUN 0x80868010
|
|
#define MSR_TMx86_LONGRUN_FLAGS 0x80868011
|
|
|
|
#define LONGRUN_MODE_MASK(x) ((x) & 0x000000007f)
|
|
#define LONGRUN_MODE_RESERVED(x) ((x) & 0xffffff80)
|
|
#define LONGRUN_MODE_WRITE(x, y) (LONGRUN_MODE_RESERVED(x) | LONGRUN_MODE_MASK(y))
|
|
|
|
#define LONGRUN_MODE_MINFREQUENCY 0x00
|
|
#define LONGRUN_MODE_ECONOMY 0x01
|
|
#define LONGRUN_MODE_PERFORMANCE 0x02
|
|
#define LONGRUN_MODE_MAXFREQUENCY 0x03
|
|
#define LONGRUN_MODE_UNKNOWN 0x04
|
|
#define LONGRUN_MODE_MAX 0x04
|
|
|
|
union msrinfo {
|
|
u_int64_t msr;
|
|
u_int32_t regs[2];
|
|
};
|
|
|
|
u_int32_t longrun_modes[LONGRUN_MODE_MAX][3] = {
|
|
/* MSR low, MSR high, flags bit0 */
|
|
{ 0, 0, 0}, /* LONGRUN_MODE_MINFREQUENCY */
|
|
{ 0, 100, 0}, /* LONGRUN_MODE_ECONOMY */
|
|
{ 0, 100, 1}, /* LONGRUN_MODE_PERFORMANCE */
|
|
{ 100, 100, 1}, /* LONGRUN_MODE_MAXFREQUENCY */
|
|
};
|
|
|
|
static u_int
|
|
tmx86_get_longrun_mode(void)
|
|
{
|
|
u_long eflags;
|
|
union msrinfo msrinfo;
|
|
u_int low, high, flags, mode;
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
|
|
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
|
|
low = LONGRUN_MODE_MASK(msrinfo.regs[0]);
|
|
high = LONGRUN_MODE_MASK(msrinfo.regs[1]);
|
|
flags = rdmsr(MSR_TMx86_LONGRUN_FLAGS) & 0x01;
|
|
|
|
for (mode = 0; mode < LONGRUN_MODE_MAX; mode++) {
|
|
if (low == longrun_modes[mode][0] &&
|
|
high == longrun_modes[mode][1] &&
|
|
flags == longrun_modes[mode][2]) {
|
|
goto out;
|
|
}
|
|
}
|
|
mode = LONGRUN_MODE_UNKNOWN;
|
|
out:
|
|
write_eflags(eflags);
|
|
return (mode);
|
|
}
|
|
|
|
static u_int
|
|
tmx86_get_longrun_status(u_int * frequency, u_int * voltage, u_int * percentage)
|
|
{
|
|
u_long eflags;
|
|
u_int regs[4];
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
|
|
do_cpuid(0x80860007, regs);
|
|
*frequency = regs[0];
|
|
*voltage = regs[1];
|
|
*percentage = regs[2];
|
|
|
|
write_eflags(eflags);
|
|
return (1);
|
|
}
|
|
|
|
static u_int
|
|
tmx86_set_longrun_mode(u_int mode)
|
|
{
|
|
u_long eflags;
|
|
union msrinfo msrinfo;
|
|
|
|
if (mode >= LONGRUN_MODE_UNKNOWN) {
|
|
return (0);
|
|
}
|
|
|
|
eflags = read_eflags();
|
|
disable_intr();
|
|
|
|
/* Write LongRun mode values to Model Specific Register. */
|
|
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN);
|
|
msrinfo.regs[0] = LONGRUN_MODE_WRITE(msrinfo.regs[0],
|
|
longrun_modes[mode][0]);
|
|
msrinfo.regs[1] = LONGRUN_MODE_WRITE(msrinfo.regs[1],
|
|
longrun_modes[mode][1]);
|
|
wrmsr(MSR_TMx86_LONGRUN, msrinfo.msr);
|
|
|
|
/* Write LongRun mode flags to Model Specific Register. */
|
|
msrinfo.msr = rdmsr(MSR_TMx86_LONGRUN_FLAGS);
|
|
msrinfo.regs[0] = (msrinfo.regs[0] & ~0x01) | longrun_modes[mode][2];
|
|
wrmsr(MSR_TMx86_LONGRUN_FLAGS, msrinfo.msr);
|
|
|
|
write_eflags(eflags);
|
|
return (1);
|
|
}
|
|
|
|
static u_int crusoe_longrun;
|
|
static u_int crusoe_frequency;
|
|
static u_int crusoe_voltage;
|
|
static u_int crusoe_percentage;
|
|
static u_int crusoe_performance_longrun = LONGRUN_MODE_PERFORMANCE;
|
|
static u_int crusoe_economy_longrun = LONGRUN_MODE_ECONOMY;
|
|
static struct sysctl_ctx_list crusoe_sysctl_ctx;
|
|
static struct sysctl_oid *crusoe_sysctl_tree;
|
|
|
|
static void
|
|
tmx86_longrun_power_profile(void *arg)
|
|
{
|
|
int state;
|
|
u_int new;
|
|
|
|
state = power_profile_get_state();
|
|
if (state != POWER_PROFILE_PERFORMANCE &&
|
|
state != POWER_PROFILE_ECONOMY) {
|
|
return;
|
|
}
|
|
|
|
switch (state) {
|
|
case POWER_PROFILE_PERFORMANCE:
|
|
new =crusoe_performance_longrun;
|
|
break;
|
|
case POWER_PROFILE_ECONOMY:
|
|
new = crusoe_economy_longrun;
|
|
break;
|
|
default:
|
|
new = tmx86_get_longrun_mode();
|
|
break;
|
|
}
|
|
|
|
if (tmx86_get_longrun_mode() != new) {
|
|
tmx86_set_longrun_mode(new);
|
|
}
|
|
}
|
|
|
|
static int
|
|
tmx86_longrun_sysctl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
u_int mode;
|
|
int error;
|
|
|
|
crusoe_longrun = tmx86_get_longrun_mode();
|
|
mode = crusoe_longrun;
|
|
error = sysctl_handle_int(oidp, &mode, 0, req);
|
|
if (error || !req->newptr) {
|
|
return (error);
|
|
}
|
|
if (mode >= LONGRUN_MODE_UNKNOWN) {
|
|
error = EINVAL;
|
|
return (error);
|
|
}
|
|
if (crusoe_longrun != mode) {
|
|
crusoe_longrun = mode;
|
|
tmx86_set_longrun_mode(crusoe_longrun);
|
|
}
|
|
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
tmx86_status_sysctl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
u_int val;
|
|
int error;
|
|
|
|
tmx86_get_longrun_status(&crusoe_frequency,
|
|
&crusoe_voltage, &crusoe_percentage);
|
|
val = *(u_int *)oidp->oid_arg1;
|
|
error = sysctl_handle_int(oidp, &val, 0, req);
|
|
return (error);
|
|
}
|
|
|
|
static int
|
|
tmx86_longrun_profile_sysctl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
u_int32_t *argp;
|
|
u_int32_t arg;
|
|
int error;
|
|
|
|
argp = (u_int32_t *)oidp->oid_arg1;
|
|
arg = *argp;
|
|
error = sysctl_handle_int(oidp, &arg, 0, req);
|
|
|
|
/* error or no new value */
|
|
if ((error != 0) || (req->newptr == NULL))
|
|
return (error);
|
|
|
|
/* range check */
|
|
if (arg >= LONGRUN_MODE_UNKNOWN)
|
|
return (EINVAL);
|
|
|
|
/* set new value and possibly switch */
|
|
*argp = arg;
|
|
|
|
tmx86_longrun_power_profile(NULL);
|
|
|
|
return (0);
|
|
|
|
}
|
|
|
|
static void
|
|
setup_tmx86_longrun(void)
|
|
{
|
|
static int done = 0;
|
|
|
|
if (done)
|
|
return;
|
|
done++;
|
|
|
|
sysctl_ctx_init(&crusoe_sysctl_ctx);
|
|
crusoe_sysctl_tree = SYSCTL_ADD_NODE(&crusoe_sysctl_ctx,
|
|
SYSCTL_STATIC_CHILDREN(_hw), OID_AUTO,
|
|
"crusoe", CTLFLAG_RD, 0,
|
|
"Transmeta Crusoe LongRun support");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "longrun", CTLTYPE_INT | CTLFLAG_RW,
|
|
&crusoe_longrun, 0, tmx86_longrun_sysctl, "I",
|
|
"LongRun mode [0-3]");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "frequency", CTLTYPE_INT | CTLFLAG_RD,
|
|
&crusoe_frequency, 0, tmx86_status_sysctl, "I",
|
|
"Current frequency (MHz)");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "voltage", CTLTYPE_INT | CTLFLAG_RD,
|
|
&crusoe_voltage, 0, tmx86_status_sysctl, "I",
|
|
"Current voltage (mV)");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "percentage", CTLTYPE_INT | CTLFLAG_RD,
|
|
&crusoe_percentage, 0, tmx86_status_sysctl, "I",
|
|
"Processing performance (%)");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "performance_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
|
|
&crusoe_performance_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
|
|
SYSCTL_ADD_PROC(&crusoe_sysctl_ctx, SYSCTL_CHILDREN(crusoe_sysctl_tree),
|
|
OID_AUTO, "economy_longrun", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_RW,
|
|
&crusoe_economy_longrun, 0, tmx86_longrun_profile_sysctl, "I", "");
|
|
|
|
/* register performance profile change handler */
|
|
EVENTHANDLER_REGISTER(power_profile_change, tmx86_longrun_power_profile, NULL, 0);
|
|
|
|
}
|
|
|
|
static void
|
|
print_transmeta_info()
|
|
{
|
|
u_int regs[4], nreg = 0;
|
|
|
|
do_cpuid(0x80860000, regs);
|
|
nreg = regs[0];
|
|
if (nreg >= 0x80860001) {
|
|
do_cpuid(0x80860001, regs);
|
|
printf(" Processor revision %u.%u.%u.%u\n",
|
|
(regs[1] >> 24) & 0xff,
|
|
(regs[1] >> 16) & 0xff,
|
|
(regs[1] >> 8) & 0xff,
|
|
regs[1] & 0xff);
|
|
}
|
|
if (nreg >= 0x80860002) {
|
|
do_cpuid(0x80860002, regs);
|
|
printf(" Code Morphing Software revision %u.%u.%u-%u-%u\n",
|
|
(regs[1] >> 24) & 0xff,
|
|
(regs[1] >> 16) & 0xff,
|
|
(regs[1] >> 8) & 0xff,
|
|
regs[1] & 0xff,
|
|
regs[2]);
|
|
}
|
|
if (nreg >= 0x80860006) {
|
|
char info[65];
|
|
do_cpuid(0x80860003, (u_int*) &info[0]);
|
|
do_cpuid(0x80860004, (u_int*) &info[16]);
|
|
do_cpuid(0x80860005, (u_int*) &info[32]);
|
|
do_cpuid(0x80860006, (u_int*) &info[48]);
|
|
info[64] = 0;
|
|
printf(" %s\n", info);
|
|
}
|
|
|
|
crusoe_longrun = tmx86_get_longrun_mode();
|
|
tmx86_get_longrun_status(&crusoe_frequency,
|
|
&crusoe_voltage, &crusoe_percentage);
|
|
printf(" LongRun mode: %d <%dMHz %dmV %d%%>\n", crusoe_longrun,
|
|
crusoe_frequency, crusoe_voltage, crusoe_percentage);
|
|
}
|
|
|
|
/*
|
|
* The AMD Elan sc520 is a system-on-chip gadget which is used in embedded
|
|
* kind of things, see www.soekris.com for instance, and it has a few quirks
|
|
* we need to deal with.
|
|
* Unfortunately we cannot identify the gadget by CPUID output because it
|
|
* depends on strapping options and only the stepping field may be useful
|
|
* and those are undocumented from AMDs side.
|
|
*
|
|
* So instead we recognize the on-chip host-PCI bridge and call back from
|
|
* sys/i386/pci/pci_bus.c to here if we find it.
|
|
*/
|
|
|
|
#include <sys/proc.h>
|
|
#include <vm/vm.h>
|
|
#include <vm/pmap.h>
|
|
|
|
uint16_t *elan_mmcr;
|
|
|
|
void
|
|
init_AMD_Elan_sc520(void)
|
|
{
|
|
u_int new;
|
|
int i;
|
|
|
|
printf("Doing h0h0magic for AMD Elan sc520\n");
|
|
elan_mmcr = pmap_mapdev(0xfffef000, 0x1000);
|
|
printf("MMCR at %p\n", elan_mmcr);
|
|
|
|
/*-
|
|
* The i8254 is driven with a nonstandard frequency which is
|
|
* derived thusly:
|
|
* f = 32768 * 45 * 25 / 31 = 1189161.29...
|
|
* We use the sysctl to get the timecounter etc into whack.
|
|
*/
|
|
|
|
new = 1189161;
|
|
i = kernel_sysctlbyname(&thread0, "machdep.i8254_freq",
|
|
NULL, 0,
|
|
&new, sizeof new,
|
|
NULL);
|
|
printf("sysctl machdep.i8254_freq=%d returns %d\n", new, i);
|
|
}
|
|
|