769 lines
17 KiB
Plaintext
769 lines
17 KiB
Plaintext
#include <dt-bindings/clock/jz4780-cgu.h>
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#include <dt-bindings/dma/jz4780-dma.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "ingenic,jz4780";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "ingenic,xburst";
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reg = <0>;
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};
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cpu1: cpu@1 {
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compatible = "ingenic,xburst";
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reg = <1>;
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clocks = <&cgu JZ4780_CLK_CORE1>;
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};
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};
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cpuintc: cpuintc@0 {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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intc: intc@10001000 {
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compatible = "ingenic,jz4780-intc";
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reg = <0x10001000 0x50>;
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interrupt-controller;
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#interrupt-cells = <1>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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};
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ext: ext {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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};
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rtc: rtc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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cgu: jz4780-cgu@10000000 {
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compatible = "ingenic,jz4780-cgu";
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reg = <0x10000000 0x100>;
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clocks = <&ext>, <&rtc>;
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clock-names = "ext", "rtc";
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#clock-cells = <1>;
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};
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gpu: jz4780-sgx@13040000 {
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compatible = "ingenic,jz4780-sgx";
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reg = <0x13040000 0x4000>;
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clocks = <&cgu JZ4780_CLK_GPU>;
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clock-names = "gpu";
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interrupt-parent = <&intc>;
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interrupts = <63>;
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};
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apb {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <>;
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tcu@0x10002000 {
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compatible = "ingenic,jz4780-tcu";
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reg = <0x10002000 0x140>;
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interrupt-parent = <&intc>;
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interrupts = <27 26 25>;
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};
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watchdog: jz47xx-watchdog@0x10002000 {
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compatible = "ingenic,jz4780-watchdog";
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reg = <0x10002000 0x100>;
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clocks = <&rtc>;
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clock-names = "rtc";
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};
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rtcdev: rtcdev@10003000 {
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compatible = "ingenic,jz4780-rtc";
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reg = <0x10003000 0x4c>;
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interrupt-parent = <&intc>;
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interrupts = <32>;
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};
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i2s: i2s@10020000 {
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compatible = "ingenic,jz4780-i2s";
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reg = <0x10020000 0x94>;
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clocks = <&cgu JZ4780_CLK_AIC>, <&cgu JZ4780_CLK_I2SPLL>;
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clock-names = "aic", "i2s";
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dmas = <&dma 0 JZ4780_DMA_I2S0_RX 0xffffffff>, <&dma JZ4780_DMA_I2S0_TX 0 0xffffffff>;
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dma-names = "rx" , "tx";
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};
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codec: codec@100200a4 {
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compatible = "ingenic,jz4780-codec";
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reg = <0x100200a4 0x8>;
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clocks = <&cgu JZ4780_CLK_I2SPLL>;
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clock-names = "i2s";
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};
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pinctrl@0x10010000 {
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compatible = "ingenic,jz4780-pinctrl";
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reg = <0x10010000 0x600>;
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gpa: gpa {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <17>;
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ingenic,pull-ups = <0x3fffffff>;
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};
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gpb: gpb {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <16>;
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ingenic,pull-downs = <0x000f0c03>;
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ingenic,pull-ups = <0xfff0030c>;
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};
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gpc: gpc {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <15>;
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ingenic,pull-ups = <0xffffffff>;
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};
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gpd: gpd {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <14>;
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ingenic,pull-downs = <0x0000b000>;
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ingenic,pull-ups = <0xffff4fff>;
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};
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gpe: gpe {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <13>;
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ingenic,pull-downs = <0x00000483>;
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ingenic,pull-ups = <0xfffffb7c>;
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};
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gpf: gpf {
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&intc>;
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interrupts = <12>;
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ingenic,pull-downs = <0x00580ff0>;
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ingenic,pull-ups = <0xffa7f00f>;
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};
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pincfg_nobias: nobias {
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bias-disable;
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};
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pincfg_pull_up: pull_up {
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bias-pull-up;
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};
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pincfg_pull_down: pull_down {
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bias-pull-down;
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};
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pinfunc_uart0: uart0 {
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pins_uart0_data: uart0-data {
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ingenic,pins = <&gpf 0 0 &pincfg_pull_up /* rxd */
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&gpf 3 0 &pincfg_nobias>; /* txd */
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};
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pins_uart0_dataplusflow: uart0-dataplusflow {
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ingenic,pins = <&gpf 0 0 &pincfg_pull_up /* rxd */
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&gpf 1 0 &pincfg_nobias /* cts */
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&gpf 2 0 &pincfg_nobias /* rts */
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&gpf 3 0 &pincfg_nobias>; /* txd */
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};
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};
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pinfunc_uart1: uart1 {
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pins_uart1_data: uart1-data {
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ingenic,pins = <&gpd 26 0 &pincfg_pull_up /* rxd */
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&gpd 28 0 &pincfg_nobias>; /* txd */
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};
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pins_uart1_dataplusflow: uart1-dataplusflow {
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ingenic,pins = <&gpd 26 0 &pincfg_pull_up /* rxd */
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&gpd 27 0 &pincfg_nobias /* cts */
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&gpd 29 0 &pincfg_nobias /* rts */
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&gpd 28 0 &pincfg_nobias>; /* txd */
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};
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};
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pinfunc_uart2: uart2 {
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pins_uart2_data: uart2-data {
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ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */
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&gpd 7 1 &pincfg_nobias>; /* txd */
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};
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pins_uart2_dataplusflow: uart2-dataplusflow {
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ingenic,pins = <&gpd 6 1 &pincfg_nobias /* rxd */
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&gpd 5 1 &pincfg_nobias /* cts */
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&gpd 4 1 &pincfg_nobias /* rts */
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&gpd 7 1 &pincfg_nobias>; /* txd */
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};
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};
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pinfunc_uart3: uart3 {
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pins_uart3_data: uart3-data {
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ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */
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&gpe 5 1 &pincfg_nobias>; /* txd */
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};
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pins_uart3_dataplusflow: uart3-dataplusflow {
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ingenic,pins = <&gpd 12 0 &pincfg_pull_down /* rxd */
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&gpe 5 1 &pincfg_nobias /* txd */
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&gpe 8 0 &pincfg_nobias /* cts */
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&gpe 9 0 &pincfg_nobias>; /* rts */
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};
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};
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pinfunc_uart4: uart4 {
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pins_uart4_data: uart4-data {
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ingenic,pins = <&gpc 20 2 &pincfg_pull_up /* rxd */
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&gpc 10 2 &pincfg_nobias>; /* txd */
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};
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};
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pinfunc_msc0: msc0 {
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pins_msc0_pa: msc0-pa {
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ingenic,pins = <&gpa 4 1 &pincfg_nobias /* d4 */
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&gpa 5 1 &pincfg_nobias /* d5 */
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&gpa 6 1 &pincfg_nobias /* d6 */
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&gpa 7 1 &pincfg_nobias /* d7 */
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&gpa 18 1 &pincfg_nobias /* clk */
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&gpa 19 1 &pincfg_nobias /* cmd */
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&gpa 20 1 &pincfg_nobias /* d0 */
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&gpa 21 1 &pincfg_nobias /* d1 */
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&gpa 22 1 &pincfg_nobias /* d2 */
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&gpa 23 1 &pincfg_nobias /* d3 */
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&gpa 24 1 &pincfg_nobias>; /* rst */
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};
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pins_msc0_pe: msc0-pe {
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ingenic,pins = <&gpe 20 0 &pincfg_nobias /* d0 */
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&gpe 21 0 &pincfg_nobias /* d1 */
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&gpe 22 0 &pincfg_nobias /* d2 */
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&gpe 23 0 &pincfg_nobias /* d3 */
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&gpe 28 0 &pincfg_nobias /* clk */
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&gpe 29 0 &pincfg_nobias>; /* cmd */
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};
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};
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pinfunc_msc1: msc1 {
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pins_msc1_pd: msc1-pd {
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ingenic,pins = <&gpd 20 0 &pincfg_nobias /* d0 */
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&gpd 21 0 &pincfg_nobias /* d1 */
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&gpd 22 0 &pincfg_nobias /* d2 */
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&gpd 23 0 &pincfg_nobias /* d3 */
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&gpd 24 0 &pincfg_nobias /* clk */
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&gpd 25 0 &pincfg_nobias>; /* cmd */
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};
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pins_msc1_pe: msc1-pe {
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ingenic,pins = <&gpe 20 1 &pincfg_nobias /* d0 */
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&gpe 21 1 &pincfg_nobias /* d1 */
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&gpe 22 1 &pincfg_nobias /* d2 */
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&gpe 23 1 &pincfg_nobias /* d3 */
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&gpe 28 1 &pincfg_nobias /* clk */
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&gpe 29 1 &pincfg_nobias>; /* cmd */
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};
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};
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pinfunc_nemc: nemc {
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pins_nemc_data: nemc-data {
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ingenic,pins = <&gpa 0 0 &pincfg_nobias /* sd0 */
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&gpa 1 0 &pincfg_nobias /* sd1 */
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&gpa 2 0 &pincfg_nobias /* sd2 */
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&gpa 3 0 &pincfg_nobias /* sd3 */
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&gpa 4 0 &pincfg_nobias /* sd4 */
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&gpa 5 0 &pincfg_nobias /* sd5 */
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&gpa 6 0 &pincfg_nobias /* sd6 */
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&gpa 7 0 &pincfg_nobias>; /* sd7 */
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};
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pins_nemc_cle_ale: nemc-cle-ale {
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ingenic,pins = <&gpb 0 0 &pincfg_nobias /* sa0_cl */
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&gpb 1 0 &pincfg_nobias>; /* sa1_al */
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};
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pins_nemc_addr: nemc-addr {
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ingenic,pins = <&gpb 0 0 &pincfg_nobias /* sa0_cl */
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&gpb 1 0 &pincfg_nobias /* sa1_al */
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&gpb 2 0 &pincfg_nobias /* sa2 */
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&gpb 3 0 &pincfg_nobias /* sa3 */
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&gpb 4 0 &pincfg_nobias /* sa4 */
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&gpb 5 0 &pincfg_nobias>; /* sa5 */
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};
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pins_nemc_rd_we: nemc-rd-we {
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ingenic,pins = <&gpa 16 0 &pincfg_nobias /* rd */
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&gpa 17 0 &pincfg_nobias>; /* we */
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};
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pins_nemc_frd_fwe: nemc-frd-fwe {
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ingenic,pins = <&gpa 18 0 &pincfg_nobias /* rd */
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&gpa 19 0 &pincfg_nobias>; /* we */
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};
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pins_nemc_cs1: nemc-cs1 {
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ingenic,pins = <&gpa 21 0 &pincfg_nobias>; /* cs1 */
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};
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pins_nemc_cs6: nemc-cs6 {
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ingenic,pins = <&gpa 26 0 &pincfg_nobias>; /* cs6 */
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};
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};
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pinfunc_i2c0: i2c0 {
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pins_i2c0_data: i2c0-data{
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ingenic,pins = <&gpd 30 0 &pincfg_nobias /* sda */
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&gpd 31 0 &pincfg_nobias>; /* sck */
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};
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};
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pinfunc_i2c1: i2c1 {
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pins_i2c1_data: i2c1-data{
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ingenic,pins = <&gpe 30 0 &pincfg_nobias /* sda */
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&gpe 31 0 &pincfg_nobias>; /* sck */
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};
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};
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pinfunc_i2c2: i2c2 {
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pins_i2c2_data: i2c2-data{
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ingenic,pins = <&gpf 16 2 &pincfg_nobias /* sda */
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&gpf 17 2 &pincfg_nobias>; /* sck */
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};
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};
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pinfunc_i2c3: i2c3 {
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pins_i2c3_data: i2c3-data{
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ingenic,pins = <&gpd 10 1 &pincfg_nobias /* sda */
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&gpd 11 1 &pincfg_nobias>; /* sck */
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};
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};
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pinfunc_i2c4: i2c4 {
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pins_i2c4_data: i2c4-data-pe{
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ingenic,pins = <&gpe 12 1 &pincfg_nobias /* sda */
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&gpe 13 1 &pincfg_nobias>; /* sck */
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};
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pins_i2c4_data_pf: i2c4-data-pf{
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ingenic,pins = <&gpf 25 1 &pincfg_nobias /* hdmi_sda */
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&gpf 24 1 &pincfg_nobias>; /* hdmi_sck */
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};
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};
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pinfunc_cim: cim {
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pins_cim: cim-pb {
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ingenic,pins = <&gpb 6 0 &pincfg_nobias
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&gpb 7 0 &pincfg_nobias
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&gpb 8 0 &pincfg_nobias
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&gpb 9 0 &pincfg_nobias
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&gpb 10 0 &pincfg_nobias
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&gpb 11 0 &pincfg_nobias
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&gpb 12 0 &pincfg_nobias
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&gpb 13 0 &pincfg_nobias
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&gpb 14 0 &pincfg_nobias
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&gpb 15 0 &pincfg_nobias
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&gpb 16 0 &pincfg_nobias
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&gpb 17 0 &pincfg_nobias>;
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};
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};
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};
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spi_gpio {
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compatible = "spi-gpio";
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#address-cells = <1>;
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#size-cells = <0>;
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num-chipselects = <2>;
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gpio-miso = <&gpe 14 0>;
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gpio-sck = <&gpe 15 0>;
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gpio-mosi = <&gpe 17 0>;
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cs-gpios = <&gpe 16 0
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&gpe 18 0>;
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spidev@0 {
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compatible = "spidev";
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reg = <0>;
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spi-max-frequency = <1000000>;
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};
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};
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uart0: serial@10030000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10030000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <51>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART0>;
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clock-names = "baud", "module";
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};
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uart1: serial@10031000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10031000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <50>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART1>;
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clock-names = "baud", "module";
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};
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uart2: serial@10032000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10032000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <49>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART2>;
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clock-names = "baud", "module";
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};
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uart3: serial@10033000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10033000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <48>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART3>;
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clock-names = "baud", "module";
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};
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uart4: serial@10034000 {
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compatible = "ingenic,jz4780-uart";
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reg = <0x10034000 0x100>;
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reg-shift = <2>;
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interrupt-parent = <&intc>;
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interrupts = <34>;
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clocks = <&ext>, <&cgu JZ4780_CLK_UART4>;
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clock-names = "baud", "module";
|
|
};
|
|
|
|
i2c0: i2c0@0x10050000 {
|
|
compatible = "ingenic,jz4780-i2c";
|
|
reg = <0x10050000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <60>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SMB0>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c1: i2c1@0x10051000 {
|
|
compatible = "ingenic,jz4780-i2c";
|
|
reg = <0x10051000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <59>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SMB1>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c2: i2c2@0x10052000 {
|
|
compatible = "ingenic,jz4780-i2c";
|
|
reg = <0x10052000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <58>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SMB2>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c3: i2c3@0x10053000 {
|
|
compatible = "ingenic,jz4780-i2c";
|
|
reg = <0x10053000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <57>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SMB3>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
i2c4: i2c4@0x10054000 {
|
|
compatible = "ingenic,jz4780-i2c";
|
|
reg = <0x10054000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <56>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SMB4>;
|
|
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
};
|
|
|
|
lpcr: lcr@0x10000004 {
|
|
compatible = "ingenic,jz4780-lcr";
|
|
reg = <0x10000004 0x4>;
|
|
|
|
regulators {
|
|
vpu_power: VPU {
|
|
};
|
|
gpu_power: GPU {
|
|
};
|
|
gps_power: GPS {
|
|
};
|
|
};
|
|
};
|
|
|
|
adc@0x10070000 {
|
|
compatible = "ingenic,jz4780-adc";
|
|
reg = <0x10070000 0x30>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <18>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_SADC>;
|
|
clock-names = "adc";
|
|
};
|
|
};
|
|
|
|
ahb2 {
|
|
compatible = "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <>;
|
|
|
|
|
|
lcd: jz4780-lcdk@0x13050000 {
|
|
compatible = "ingenic,jz4780-lcd";
|
|
reg = <0x13050000 0x1800>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_TVE>, <&cgu JZ4780_CLK_LCD0PIXCLK>;
|
|
clock-names = "lcd_clk", "lcd_pixclk";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <31>;
|
|
|
|
hdmi = <&hdmi>;
|
|
ddc = <&i2c4>;
|
|
};
|
|
|
|
cim: jz4780-cim@0x13060000 {
|
|
compatible = "ingenic,jz4780-cim";
|
|
reg = <0x13060000 0x68>;
|
|
reg-shift = <2>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <30>;
|
|
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pins_cim>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_CIM>, <&cgu JZ4780_CLK_CIMMCLK>;
|
|
clock-names = "cim", "module";
|
|
};
|
|
|
|
hdmi: jz4780-hdmi3@0x10180000 {
|
|
compatible = "synopsys,dwc-hdmi";
|
|
reg = <0x10180000 0x8000>;
|
|
reg-shift = <2>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_AHB0>;
|
|
clock-names = "hdmi" , "ahb";
|
|
|
|
clock-frequency = <27000000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <3>;
|
|
|
|
ddc = <&i2c4>;
|
|
};
|
|
|
|
|
|
nemc: nemc@13410000 {
|
|
compatible = "ingenic,jz4780-nemc";
|
|
reg = <0x13410000 0x10000>;
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
ranges = <1 0 0x1b000000 0x1000000
|
|
2 0 0x1a000000 0x1000000
|
|
3 0 0x19000000 0x1000000
|
|
4 0 0x18000000 0x1000000
|
|
5 0 0x17000000 0x1000000
|
|
6 0 0x16000000 0x1000000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_NEMC>;
|
|
};
|
|
|
|
efuse: efuse@134100D0 {
|
|
compatible = "ingenic,jz4780-efuse";
|
|
reg = <0x134100D0 0xFF>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_AHB2>;
|
|
clock-names = "bus_clk";
|
|
};
|
|
|
|
dma: dma@13420000 {
|
|
compatible = "ingenic,jz4780-dma";
|
|
reg = <0x13420000 0x10000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <10>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_PDMA>;
|
|
|
|
#dma-cells = <3>;
|
|
};
|
|
|
|
msc0: msc@13450000 {
|
|
compatible = "ingenic,jz4780-mmc";
|
|
reg = <0x13450000 0x1000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <37>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_MSC0>;
|
|
clock-names = "mmc";
|
|
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
cap-sdio-irq;
|
|
|
|
dmas = <&dma JZ4780_DMA_MSC0_TX JZ4780_DMA_MSC0_RX 0xffffffff>;
|
|
dma-names = "rx-tx";
|
|
};
|
|
|
|
msc1: msc@13460000 {
|
|
compatible = "ingenic,jz4780-mmc";
|
|
reg = <0x13460000 0x1000>;
|
|
|
|
status = "disabled";
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <36>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_MSC1>;
|
|
clock-names = "mmc";
|
|
|
|
cap-sd-highspeed;
|
|
cap-mmc-highspeed;
|
|
cap-sdio-irq;
|
|
|
|
dmas = <&dma JZ4780_DMA_MSC1_TX JZ4780_DMA_MSC1_RX 0xffffffff>;
|
|
dma-names = "rx-tx";
|
|
};
|
|
|
|
ehci: jz4780-ehci@0x13490000 {
|
|
compatible = "ingenic,jz4780-ehci";
|
|
reg = <0x13490000 0x10000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <20>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_UHC>;
|
|
};
|
|
|
|
ohci: jz4780-ohci@0x134a0000 {
|
|
compatible = "ingenic,jz4780-ohci";
|
|
reg = <0x134a0000 0x10000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <5>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_UHC>;
|
|
clock-names = "uhc";
|
|
};
|
|
|
|
bch: bch@134d0000 {
|
|
compatible = "ingenic,jz4780-bch";
|
|
reg = <0x134d0000 0x10000>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_BCH>;
|
|
};
|
|
|
|
otg: jz4780-otg@0x13500000 {
|
|
compatible = "ingenic,jz4780-otg";
|
|
reg = <0x13500000 0x40000>;
|
|
|
|
interrupt-parent = <&intc>;
|
|
interrupts = <21>;
|
|
|
|
clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_OTG1>;
|
|
clock-names = "otg_phy", "otg1";
|
|
};
|
|
};
|
|
};
|