734 lines
20 KiB
C
734 lines
20 KiB
C
/* $OpenBSD: if_iwm.c,v 1.39 2015/03/23 00:35:19 jsg Exp $ */
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/*
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* Copyright (c) 2014 genua mbh <info@genua.de>
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* Copyright (c) 2014 Fixup Software Ltd.
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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/*-
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* Based on BSD-licensed source modules in the Linux iwlwifi driver,
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* which were used as the reference documentation for this implementation.
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*
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* Driver version we are currently based off of is
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* Linux 3.14.3 (tag id a2df521e42b1d9a23f620ac79dbfe8655a8391dd)
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*
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***********************************************************************
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*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright(c) 2007 - 2013 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110,
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* USA
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*
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* The full GNU General Public License is included in this distribution
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* in the file called COPYING.
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*
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* Contact Information:
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* Intel Linux Wireless <ilw@linux.intel.com>
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* Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*
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*
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* BSD LICENSE
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*
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* Copyright(c) 2005 - 2013 Intel Corporation. All rights reserved.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name Intel Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/*-
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* Copyright (c) 2007-2010 Damien Bergamini <damien.bergamini@free.fr>
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*
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* Permission to use, copy, modify, and distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_wlan.h"
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#include "opt_iwm.h"
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/firmware.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/mbuf.h>
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#include <sys/mutex.h>
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#include <sys/module.h>
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#include <sys/proc.h>
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#include <sys/rman.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/linker.h>
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#include <machine/bus.h>
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#include <machine/endian.h>
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#include <machine/resource.h>
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#include <dev/pci/pcivar.h>
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#include <dev/pci/pcireg.h>
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#include <net/bpf.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <netinet/in.h>
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#include <netinet/in_systm.h>
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#include <netinet/if_ether.h>
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#include <netinet/ip.h>
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#include <net80211/ieee80211_var.h>
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#include <net80211/ieee80211_regdomain.h>
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#include <net80211/ieee80211_ratectl.h>
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#include <net80211/ieee80211_radiotap.h>
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#include <dev/iwm/if_iwmreg.h>
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#include <dev/iwm/if_iwmvar.h>
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#include <dev/iwm/if_iwm_config.h>
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#include <dev/iwm/if_iwm_debug.h>
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#include <dev/iwm/if_iwm_pcie_trans.h>
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/*
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* This is a subset of what's in linux iwlwifi/pcie/trans.c.
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* The rest can be migrated out into here once they're no longer in
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* if_iwm.c.
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*/
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/*
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* basic device access
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*/
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uint32_t
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iwm_read_prph(struct iwm_softc *sc, uint32_t addr)
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{
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IWM_WRITE(sc,
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IWM_HBUS_TARG_PRPH_RADDR, ((addr & 0x000fffff) | (3 << 24)));
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IWM_BARRIER_READ_WRITE(sc);
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return IWM_READ(sc, IWM_HBUS_TARG_PRPH_RDAT);
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}
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void
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iwm_write_prph(struct iwm_softc *sc, uint32_t addr, uint32_t val)
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{
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IWM_WRITE(sc,
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IWM_HBUS_TARG_PRPH_WADDR, ((addr & 0x000fffff) | (3 << 24)));
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IWM_BARRIER_WRITE(sc);
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IWM_WRITE(sc, IWM_HBUS_TARG_PRPH_WDAT, val);
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}
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void
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iwm_write_prph64(struct iwm_softc *sc, uint64_t addr, uint64_t val)
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{
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iwm_write_prph(sc, (uint32_t)addr, val & 0xffffffff);
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iwm_write_prph(sc, (uint32_t)addr + 4, val >> 32);
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}
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int
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iwm_poll_prph(struct iwm_softc *sc, uint32_t addr, uint32_t bits, uint32_t mask,
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int timeout)
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{
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do {
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if ((iwm_read_prph(sc, addr) & mask) == (bits & mask))
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return (0);
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DELAY(10);
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timeout -= 10;
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} while (timeout > 0);
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return (ETIMEDOUT);
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}
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#ifdef IWM_DEBUG
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/* iwlwifi: pcie/trans.c */
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int
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iwm_read_mem(struct iwm_softc *sc, uint32_t addr, void *buf, int dwords)
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{
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int offs, ret = 0;
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uint32_t *vals = buf;
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if (iwm_nic_lock(sc)) {
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IWM_WRITE(sc, IWM_HBUS_TARG_MEM_RADDR, addr);
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for (offs = 0; offs < dwords; offs++)
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vals[offs] = IWM_READ(sc, IWM_HBUS_TARG_MEM_RDAT);
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iwm_nic_unlock(sc);
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} else {
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ret = EBUSY;
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}
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return ret;
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}
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#endif
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/* iwlwifi: pcie/trans.c */
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int
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iwm_write_mem(struct iwm_softc *sc, uint32_t addr, const void *buf, int dwords)
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{
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int offs;
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const uint32_t *vals = buf;
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if (iwm_nic_lock(sc)) {
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IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WADDR, addr);
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/* WADDR auto-increments */
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for (offs = 0; offs < dwords; offs++) {
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uint32_t val = vals ? vals[offs] : 0;
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IWM_WRITE(sc, IWM_HBUS_TARG_MEM_WDAT, val);
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}
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iwm_nic_unlock(sc);
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} else {
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IWM_DPRINTF(sc, IWM_DEBUG_TRANS,
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"%s: write_mem failed\n", __func__);
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return EBUSY;
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}
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return 0;
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}
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int
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iwm_write_mem32(struct iwm_softc *sc, uint32_t addr, uint32_t val)
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{
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return iwm_write_mem(sc, addr, &val, 1);
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}
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int
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iwm_poll_bit(struct iwm_softc *sc, int reg,
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uint32_t bits, uint32_t mask, int timo)
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{
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for (;;) {
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if ((IWM_READ(sc, reg) & mask) == (bits & mask)) {
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return 1;
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}
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if (timo < 10) {
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return 0;
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}
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timo -= 10;
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DELAY(10);
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}
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}
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int
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iwm_nic_lock(struct iwm_softc *sc)
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{
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int rv = 0;
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if (sc->cmd_hold_nic_awake)
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return 1;
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IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
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IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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if (sc->cfg->device_family >= IWM_DEVICE_FAMILY_8000)
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DELAY(2);
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if (iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
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IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
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IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY
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| IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP, 15000)) {
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rv = 1;
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} else {
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/* jolt */
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IWM_DPRINTF(sc, IWM_DEBUG_RESET,
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"%s: resetting device via NMI\n", __func__);
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IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_FORCE_NMI);
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}
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return rv;
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}
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void
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iwm_nic_unlock(struct iwm_softc *sc)
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{
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if (sc->cmd_hold_nic_awake)
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return;
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IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
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IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
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}
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void
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iwm_set_bits_mask_prph(struct iwm_softc *sc,
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uint32_t reg, uint32_t bits, uint32_t mask)
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{
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uint32_t val;
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/* XXX: no error path? */
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if (iwm_nic_lock(sc)) {
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val = iwm_read_prph(sc, reg) & mask;
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val |= bits;
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iwm_write_prph(sc, reg, val);
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iwm_nic_unlock(sc);
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}
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}
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void
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iwm_set_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
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{
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iwm_set_bits_mask_prph(sc, reg, bits, ~0);
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}
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void
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iwm_clear_bits_prph(struct iwm_softc *sc, uint32_t reg, uint32_t bits)
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{
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iwm_set_bits_mask_prph(sc, reg, 0, ~bits);
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}
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/*
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* High-level hardware frobbing routines
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*/
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void
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iwm_enable_rfkill_int(struct iwm_softc *sc)
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{
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sc->sc_intmask = IWM_CSR_INT_BIT_RF_KILL;
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IWM_WRITE(sc, IWM_CSR_INT_MASK, sc->sc_intmask);
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IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
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IWM_CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN);
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}
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int
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iwm_check_rfkill(struct iwm_softc *sc)
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{
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uint32_t v;
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int rv;
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/*
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* "documentation" is not really helpful here:
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* 27: HW_RF_KILL_SW
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* Indicates state of (platform's) hardware RF-Kill switch
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*
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* But apparently when it's off, it's on ...
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*/
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v = IWM_READ(sc, IWM_CSR_GP_CNTRL);
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rv = (v & IWM_CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) == 0;
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if (rv) {
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sc->sc_flags |= IWM_FLAG_RFKILL;
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} else {
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sc->sc_flags &= ~IWM_FLAG_RFKILL;
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}
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return rv;
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}
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#define IWM_HW_READY_TIMEOUT 50
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int
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iwm_set_hw_ready(struct iwm_softc *sc)
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{
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int ready;
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IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
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IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY);
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ready = iwm_poll_bit(sc, IWM_CSR_HW_IF_CONFIG_REG,
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IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
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IWM_CSR_HW_IF_CONFIG_REG_BIT_NIC_READY,
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IWM_HW_READY_TIMEOUT);
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if (ready) {
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IWM_SETBITS(sc, IWM_CSR_MBOX_SET_REG,
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IWM_CSR_MBOX_SET_REG_OS_ALIVE);
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}
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return ready;
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}
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#undef IWM_HW_READY_TIMEOUT
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int
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iwm_prepare_card_hw(struct iwm_softc *sc)
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{
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int rv = 0;
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int t = 0;
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IWM_DPRINTF(sc, IWM_DEBUG_RESET, "->%s\n", __func__);
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if (iwm_set_hw_ready(sc))
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goto out;
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IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
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IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
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DELAY(1000);
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/* If HW is not ready, prepare the conditions to check again */
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IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
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IWM_CSR_HW_IF_CONFIG_REG_PREPARE);
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do {
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if (iwm_set_hw_ready(sc))
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goto out;
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DELAY(200);
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t += 200;
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} while (t < 150000);
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rv = ETIMEDOUT;
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out:
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IWM_DPRINTF(sc, IWM_DEBUG_RESET, "<-%s\n", __func__);
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return rv;
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}
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void
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iwm_apm_config(struct iwm_softc *sc)
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{
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uint16_t lctl, cap;
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int pcie_ptr;
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/*
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* HW bug W/A for instability in PCIe bus L0S->L1 transition.
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* Check if BIOS (or OS) enabled L1-ASPM on this device.
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* If so (likely), disable L0S, so device moves directly L0->L1;
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* costs negligible amount of power savings.
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* If not (unlikely), enable L0S, so there is at least some
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* power savings, even without L1.
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*/
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int error;
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error = pci_find_cap(sc->sc_dev, PCIY_EXPRESS, &pcie_ptr);
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if (error != 0)
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return;
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lctl = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_LINK_CTL,
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sizeof(lctl));
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if (lctl & PCIEM_LINK_CTL_ASPMC_L1) {
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IWM_SETBITS(sc, IWM_CSR_GIO_REG,
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IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
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} else {
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IWM_CLRBITS(sc, IWM_CSR_GIO_REG,
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IWM_CSR_GIO_REG_VAL_L0S_ENABLED);
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}
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cap = pci_read_config(sc->sc_dev, pcie_ptr + PCIER_DEVICE_CTL2,
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sizeof(cap));
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sc->sc_ltr_enabled = (cap & PCIEM_CTL2_LTR_ENABLE) ? 1 : 0;
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IWM_DPRINTF(sc, IWM_DEBUG_RESET | IWM_DEBUG_PWRSAVE,
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"L1 %sabled - LTR %sabled\n",
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(lctl & PCIEM_LINK_CTL_ASPMC_L1) ? "En" : "Dis",
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sc->sc_ltr_enabled ? "En" : "Dis");
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}
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/*
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* Start up NIC's basic functionality after it has been reset
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* (e.g. after platform boot, or shutdown via iwm_pcie_apm_stop())
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* NOTE: This does not load uCode nor start the embedded processor
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*/
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int
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iwm_apm_init(struct iwm_softc *sc)
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{
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int error = 0;
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IWM_DPRINTF(sc, IWM_DEBUG_RESET, "iwm apm start\n");
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|
|
/* Disable L0S exit timer (platform NMI Work/Around) */
|
|
if (sc->cfg->device_family < IWM_DEVICE_FAMILY_8000) {
|
|
IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
|
|
IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
|
|
}
|
|
|
|
/*
|
|
* Disable L0s without affecting L1;
|
|
* don't wait for ICH L0s (ICH bug W/A)
|
|
*/
|
|
IWM_SETBITS(sc, IWM_CSR_GIO_CHICKEN_BITS,
|
|
IWM_CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
|
|
|
|
/* Set FH wait threshold to maximum (HW error during stress W/A) */
|
|
IWM_SETBITS(sc, IWM_CSR_DBG_HPET_MEM_REG, IWM_CSR_DBG_HPET_MEM_REG_VAL);
|
|
|
|
/*
|
|
* Enable HAP INTA (interrupt from management bus) to
|
|
* wake device's PCI Express link L1a -> L0s
|
|
*/
|
|
IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
|
|
IWM_CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
|
|
|
|
iwm_apm_config(sc);
|
|
|
|
#if 0 /* not for 7k/8k */
|
|
/* Configure analog phase-lock-loop before activating to D0A */
|
|
if (trans->cfg->base_params->pll_cfg_val)
|
|
IWM_SETBITS(trans, IWM_CSR_ANA_PLL_CFG,
|
|
trans->cfg->base_params->pll_cfg_val);
|
|
#endif
|
|
|
|
/*
|
|
* Set "initialization complete" bit to move adapter from
|
|
* D0U* --> D0A* (powered-up active) state.
|
|
*/
|
|
IWM_SETBITS(sc, IWM_CSR_GP_CNTRL, IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
|
|
|
/*
|
|
* Wait for clock stabilization; once stabilized, access to
|
|
* device-internal resources is supported, e.g. iwm_write_prph()
|
|
* and accesses to uCode SRAM.
|
|
*/
|
|
if (!iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000)) {
|
|
device_printf(sc->sc_dev,
|
|
"timeout waiting for clock stabilization\n");
|
|
error = ETIMEDOUT;
|
|
goto out;
|
|
}
|
|
|
|
if (sc->cfg->host_interrupt_operation_mode) {
|
|
/*
|
|
* This is a bit of an abuse - This is needed for 7260 / 3160
|
|
* only check host_interrupt_operation_mode even if this is
|
|
* not related to host_interrupt_operation_mode.
|
|
*
|
|
* Enable the oscillator to count wake up time for L1 exit. This
|
|
* consumes slightly more power (100uA) - but allows to be sure
|
|
* that we wake up from L1 on time.
|
|
*
|
|
* This looks weird: read twice the same register, discard the
|
|
* value, set a bit, and yet again, read that same register
|
|
* just to discard the value. But that's the way the hardware
|
|
* seems to like it.
|
|
*/
|
|
if (iwm_nic_lock(sc)) {
|
|
iwm_read_prph(sc, IWM_OSC_CLK);
|
|
iwm_read_prph(sc, IWM_OSC_CLK);
|
|
iwm_nic_unlock(sc);
|
|
}
|
|
iwm_set_bits_prph(sc, IWM_OSC_CLK, IWM_OSC_CLK_FORCE_CONTROL);
|
|
if (iwm_nic_lock(sc)) {
|
|
iwm_read_prph(sc, IWM_OSC_CLK);
|
|
iwm_read_prph(sc, IWM_OSC_CLK);
|
|
iwm_nic_unlock(sc);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Enable DMA clock and wait for it to stabilize.
|
|
*
|
|
* Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" bits
|
|
* do not disable clocks. This preserves any hardware bits already
|
|
* set by default in "CLK_CTRL_REG" after reset.
|
|
*/
|
|
if (sc->cfg->device_family == IWM_DEVICE_FAMILY_7000) {
|
|
if (iwm_nic_lock(sc)) {
|
|
iwm_write_prph(sc, IWM_APMG_CLK_EN_REG,
|
|
IWM_APMG_CLK_VAL_DMA_CLK_RQT);
|
|
iwm_nic_unlock(sc);
|
|
}
|
|
DELAY(20);
|
|
|
|
/* Disable L1-Active */
|
|
iwm_set_bits_prph(sc, IWM_APMG_PCIDEV_STT_REG,
|
|
IWM_APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
|
|
|
|
/* Clear the interrupt in APMG if the NIC is in RFKILL */
|
|
if (iwm_nic_lock(sc)) {
|
|
iwm_write_prph(sc, IWM_APMG_RTC_INT_STT_REG,
|
|
IWM_APMG_RTC_INT_STT_RFKILL);
|
|
iwm_nic_unlock(sc);
|
|
}
|
|
}
|
|
out:
|
|
if (error)
|
|
device_printf(sc->sc_dev, "apm init error %d\n", error);
|
|
return error;
|
|
}
|
|
|
|
/* iwlwifi/pcie/trans.c */
|
|
void
|
|
iwm_apm_stop(struct iwm_softc *sc)
|
|
{
|
|
IWM_SETBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
|
|
IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
|
|
IWM_SETBITS(sc, IWM_CSR_HW_IF_CONFIG_REG,
|
|
IWM_CSR_HW_IF_CONFIG_REG_PREPARE |
|
|
IWM_CSR_HW_IF_CONFIG_REG_ENABLE_PME);
|
|
DELAY(1000);
|
|
IWM_CLRBITS(sc, IWM_CSR_DBG_LINK_PWR_MGMT_REG,
|
|
IWM_CSR_RESET_LINK_PWR_MGMT_DISABLED);
|
|
DELAY(5000);
|
|
|
|
/* stop device's busmaster DMA activity */
|
|
IWM_SETBITS(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_STOP_MASTER);
|
|
|
|
if (!iwm_poll_bit(sc, IWM_CSR_RESET,
|
|
IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED,
|
|
IWM_CSR_RESET_REG_FLAG_MASTER_DISABLED, 100))
|
|
device_printf(sc->sc_dev, "timeout waiting for master\n");
|
|
|
|
/*
|
|
* Clear "initialization complete" bit to move adapter from
|
|
* D0A* (powered-up Active) --> D0U* (Uninitialized) state.
|
|
*/
|
|
IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
|
|
|
|
IWM_DPRINTF(sc, IWM_DEBUG_TRANS, "%s: iwm apm stop\n", __func__);
|
|
}
|
|
|
|
/* iwlwifi pcie/trans.c */
|
|
int
|
|
iwm_start_hw(struct iwm_softc *sc)
|
|
{
|
|
int error;
|
|
|
|
if ((error = iwm_prepare_card_hw(sc)) != 0)
|
|
return error;
|
|
|
|
/* Reset the entire device */
|
|
IWM_WRITE(sc, IWM_CSR_RESET, IWM_CSR_RESET_REG_FLAG_SW_RESET);
|
|
DELAY(5000);
|
|
|
|
if ((error = iwm_apm_init(sc)) != 0)
|
|
return error;
|
|
|
|
/* On newer chipsets MSI is disabled by default. */
|
|
if (sc->cfg->mqrx_supported)
|
|
iwm_write_prph(sc, IWM_UREG_CHICK, IWM_UREG_CHICK_MSI_ENABLE);
|
|
|
|
iwm_enable_rfkill_int(sc);
|
|
iwm_check_rfkill(sc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/* iwlwifi pcie/trans.c (always main power) */
|
|
void
|
|
iwm_set_pwr(struct iwm_softc *sc)
|
|
{
|
|
iwm_set_bits_mask_prph(sc, IWM_APMG_PS_CTRL_REG,
|
|
IWM_APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, ~IWM_APMG_PS_CTRL_MSK_PWR_SRC);
|
|
}
|
|
|
|
/* iwlwifi pcie/rx.c */
|
|
int
|
|
iwm_pcie_rx_stop(struct iwm_softc *sc)
|
|
{
|
|
int ret;
|
|
|
|
ret = 0;
|
|
if (iwm_nic_lock(sc)) {
|
|
if (sc->cfg->mqrx_supported) {
|
|
iwm_write_prph(sc, IWM_RFH_RXF_DMA_CFG, 0);
|
|
ret = iwm_poll_prph(sc, IWM_RFH_GEN_STATUS,
|
|
IWM_RXF_DMA_IDLE, IWM_RXF_DMA_IDLE, 1000);
|
|
} else {
|
|
IWM_WRITE(sc, IWM_FH_MEM_RCSR_CHNL0_CONFIG_REG, 0);
|
|
ret = iwm_poll_bit(sc, IWM_FH_MEM_RSSR_RX_STATUS_REG,
|
|
IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
|
|
IWM_FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE,
|
|
1000);
|
|
}
|
|
iwm_nic_unlock(sc);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
void
|
|
iwm_pcie_clear_cmd_in_flight(struct iwm_softc *sc)
|
|
{
|
|
if (!sc->cfg->apmg_wake_up_wa)
|
|
return;
|
|
|
|
if (!sc->cmd_hold_nic_awake) {
|
|
device_printf(sc->sc_dev,
|
|
"%s: cmd_hold_nic_awake not set\n", __func__);
|
|
return;
|
|
}
|
|
|
|
sc->cmd_hold_nic_awake = 0;
|
|
IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
|
}
|
|
|
|
int
|
|
iwm_pcie_set_cmd_in_flight(struct iwm_softc *sc)
|
|
{
|
|
int ret;
|
|
|
|
/*
|
|
* wake up the NIC to make sure that the firmware will see the host
|
|
* command - we will let the NIC sleep once all the host commands
|
|
* returned. This needs to be done only on NICs that have
|
|
* apmg_wake_up_wa set.
|
|
*/
|
|
if (sc->cfg->apmg_wake_up_wa &&
|
|
!sc->cmd_hold_nic_awake) {
|
|
|
|
IWM_SETBITS(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
|
|
|
ret = iwm_poll_bit(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
|
|
(IWM_CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP),
|
|
15000);
|
|
if (ret == 0) {
|
|
IWM_CLRBITS(sc, IWM_CSR_GP_CNTRL,
|
|
IWM_CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
|
|
device_printf(sc->sc_dev,
|
|
"%s: Failed to wake NIC for hcmd\n", __func__);
|
|
return EIO;
|
|
}
|
|
sc->cmd_hold_nic_awake = 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|