d4fcf3cba5
and amd64. The optimization is a trivial on recent machines. Reviewed by: -arch (imp, marcel, dfr)
198 lines
5.1 KiB
C
198 lines
5.1 KiB
C
/*-
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* Copyright (c) 2000 Matthew N. Dodd <winter@jurai.net>
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* All rights reserved.
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*
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* Copyright (c) 1997 Simon Shapiro
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* All Rights Reserved
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <sys/rman.h>
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#include <dev/pci/pcireg.h>
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#include <dev/pci/pcivar.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/dpt/dpt.h>
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#define DPT_VENDOR_ID 0x1044
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#define DPT_DEVICE_ID 0xa400
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#define DPT_PCI_IOADDR PCIR_BAR(0) /* I/O Address */
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#define DPT_PCI_MEMADDR PCIR_BAR(1) /* Mem I/O Address */
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#define ISA_PRIMARY_WD_ADDRESS 0x1f8
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static int dpt_pci_probe (device_t);
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static int dpt_pci_attach (device_t);
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static int
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dpt_pci_probe (device_t dev)
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{
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if ((pci_get_vendor(dev) == DPT_VENDOR_ID) &&
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(pci_get_device(dev) == DPT_DEVICE_ID)) {
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device_set_desc(dev, "DPT Caching SCSI RAID Controller");
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return (BUS_PROBE_DEFAULT);
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}
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return (ENXIO);
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}
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static int
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dpt_pci_attach (device_t dev)
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{
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dpt_softc_t * dpt;
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int s;
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int error = 0;
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u_int32_t command;
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dpt = device_get_softc(dev);
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command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
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#ifdef DPT_ALLOW_MMIO
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if ((command & PCIM_CMD_MEMEN) != 0) {
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dpt->io_rid = DPT_PCI_MEMADDR;
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dpt->io_type = SYS_RES_MEMORY;
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dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
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&dpt->io_rid, RF_ACTIVE);
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}
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#endif
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if (dpt->io_res == NULL && (command & PCIM_CMD_PORTEN) != 0) {
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dpt->io_rid = DPT_PCI_IOADDR;
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dpt->io_type = SYS_RES_IOPORT;
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dpt->io_res = bus_alloc_resource_any(dev, dpt->io_type,
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&dpt->io_rid, RF_ACTIVE);
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}
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if (dpt->io_res == NULL) {
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device_printf(dev, "can't allocate register resources\n");
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error = ENOMEM;
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goto bad;
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}
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dpt->io_offset = 0x10;
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dpt->irq_rid = 0;
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dpt->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &dpt->irq_rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (dpt->irq_res == NULL) {
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device_printf(dev, "No irq?!\n");
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error = ENOMEM;
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goto bad;
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}
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/* Ensure busmastering is enabled */
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command |= PCIM_CMD_BUSMASTEREN;
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pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
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if (rman_get_start(dpt->io_res) == (ISA_PRIMARY_WD_ADDRESS - 0x10)) {
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#ifdef DPT_DEBUG_WARN
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device_printf(dev, "Mapped as an IDE controller. "
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"Disabling SCSI setup\n");
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#endif
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error = ENXIO;
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goto bad;
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}
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dpt_alloc(dev);
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/* Allocate a dmatag representing the capabilities of this attachment */
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/* XXX Should be a child of the PCI bus dma tag */
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if (bus_dma_tag_create( /* parent */ NULL,
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/* alignemnt */ 1,
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/* boundary */ 0,
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/* lowaddr */ BUS_SPACE_MAXADDR_32BIT,
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/* highaddr */ BUS_SPACE_MAXADDR,
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/* filter */ NULL,
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/* filterarg */ NULL,
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/* maxsize */ BUS_SPACE_MAXSIZE_32BIT,
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/* nsegments */ ~0,
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/* maxsegsz */ BUS_SPACE_MAXSIZE_32BIT,
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/* flags */ 0,
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/* lockfunc */ busdma_lock_mutex,
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/* lockarg */ &Giant,
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&dpt->parent_dmat) != 0) {
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error = ENXIO;
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goto bad;
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}
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s = splcam();
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if (dpt_init(dpt) != 0) {
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error = ENXIO;
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goto bad;
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}
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/* Register with the XPT */
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dpt_attach(dpt);
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splx(s);
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if (bus_setup_intr(dev, dpt->irq_res, INTR_TYPE_CAM | INTR_ENTROPY,
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dpt_intr, dpt, &dpt->ih)) {
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device_printf(dev, "Unable to register interrupt handler\n");
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error = ENXIO;
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goto bad;
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}
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return (error);
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bad:
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dpt_release_resources(dev);
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dpt_free(dpt);
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return (error);
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}
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static device_method_t dpt_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, dpt_pci_probe),
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DEVMETHOD(device_attach, dpt_pci_attach),
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DEVMETHOD(device_detach, dpt_detach),
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{ 0, 0 }
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};
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static driver_t dpt_pci_driver = {
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"dpt",
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dpt_pci_methods,
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sizeof(dpt_softc_t),
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};
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DRIVER_MODULE(dpt, pci, dpt_pci_driver, dpt_devclass, 0, 0);
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