This fixes the race when first core sets up the pagetables, while secondary cores do translating the address of __riscv_boot_ap. This now allows us to smpboot in QEMU with 8 cores just fine. Sponsored by: DARPA, AFRL |
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conf | ||
include | ||
riscv |
This fixes the race when first core sets up the pagetables, while secondary cores do translating the address of __riscv_boot_ap. This now allows us to smpboot in QEMU with 8 cores just fine. Sponsored by: DARPA, AFRL |
||
---|---|---|
.. | ||
conf | ||
include | ||
riscv |