686 lines
21 KiB
C
686 lines
21 KiB
C
/*-
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* Copyright (c) 2001 Michael Smith
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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/*
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* Structure and I/O definitions for the Command Interface for SCSI-3 Support.
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*
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* Data in command CDBs are in big-endian format. All other data is little-endian.
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* This header only supports little-endian hosts at this time.
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*/
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union ciss_device_address
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{
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struct /* MODE_PERIPHERAL and MODE_MASK_PERIPHERAL */
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{
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u_int32_t target:24; /* SCSI target */
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u_int32_t bus:6; /* SCSI bus */
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u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_* */
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u_int32_t extra_address; /* SCSI-3 level-2 and level-3 address bytes */
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} physical;
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struct /* MODE_LOGICAL */
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{
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u_int32_t lun:30; /* logical device ID */
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u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_LOGICAL */
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u_int32_t :32; /* reserved */
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} logical;
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struct
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{
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u_int32_t :30;
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u_int32_t mode:2;
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u_int32_t :32;
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} mode;
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};
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#define CISS_HDR_ADDRESS_MODE_PERIPHERAL 0x0
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#define CISS_HDR_ADDRESS_MODE_LOGICAL 0x1
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#define CISS_HDR_ADDRESS_MODE_MASK_PERIPHERAL 0x3
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struct ciss_header
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{
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u_int8_t :8; /* reserved */
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u_int8_t sg_in_list; /* SG's in the command structure */
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u_int16_t sg_total; /* total count of SGs for this command */
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u_int32_t host_tag; /* host identifier, bits 0&1 must be clear */
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#define CISS_HDR_HOST_TAG_ERROR (1<<1)
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u_int32_t host_tag_zeroes; /* tag is 64 bits, but interface only supports 32 */
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union ciss_device_address address;
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} __packed;
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struct ciss_cdb
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{
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u_int8_t cdb_length; /* valid CDB bytes */
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u_int8_t type:3;
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#define CISS_CDB_TYPE_COMMAND 0
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#define CISS_CDB_TYPE_MESSAGE 1
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u_int8_t attribute:3;
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#define CISS_CDB_ATTRIBUTE_UNTAGGED 0
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#define CISS_CDB_ATTRIBUTE_SIMPLE 4
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#define CISS_CDB_ATTRIBUTE_HEAD_OF_QUEUE 5
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#define CISS_CDB_ATTRIBUTE_ORDERED 6
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#define CISS_CDB_ATTRIBUTE_AUTO_CONTINGENT 7
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u_int8_t direction:2;
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#define CISS_CDB_DIRECTION_NONE 0
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#define CISS_CDB_DIRECTION_READ 1
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#define CISS_CDB_DIRECTION_WRITE 2
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u_int16_t timeout; /* seconds */
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#define CISS_CDB_BUFFER_SIZE 16
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u_int8_t cdb[CISS_CDB_BUFFER_SIZE];
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} __packed;
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struct ciss_error_info_pointer
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{
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u_int64_t error_info_address; /* points to ciss_error_info structure */
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u_int32_t error_info_length;
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} __packed;
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struct ciss_error_info
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{
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u_int8_t scsi_status;
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#define CISS_SCSI_STATUS_GOOD 0x00 /* these are scsi-standard values */
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#define CISS_SCSI_STATUS_CHECK_CONDITION 0x02
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#define CISS_SCSI_STATUS_CONDITION_MET 0x04
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#define CISS_SCSI_STATUS_BUSY 0x08
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#define CISS_SCSI_STATUS_INDETERMINATE 0x10
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#define CISS_SCSI_STATUS_INDETERMINATE_CM 0x14
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#define CISS_SCSI_STATUS_RESERVATION_CONFLICT 0x18
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#define CISS_SCSI_STATUS_COMMAND_TERMINATED 0x22
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#define CISS_SCSI_STATUS_QUEUE_FULL 0x28
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#define CISS_SCSI_STATUS_ACA_ACTIVE 0x30
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u_int8_t sense_length;
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u_int16_t command_status;
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#define CISS_CMD_STATUS_SUCCESS 0
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#define CISS_CMD_STATUS_TARGET_STATUS 1
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#define CISS_CMD_STATUS_DATA_UNDERRUN 2
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#define CISS_CMD_STATUS_DATA_OVERRUN 3
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#define CISS_CMD_STATUS_INVALID_COMMAND 4
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#define CISS_CMD_STATUS_PROTOCOL_ERROR 5
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#define CISS_CMD_STATUS_HARDWARE_ERROR 6
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#define CISS_CMD_STATUS_CONNECTION_LOST 7
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#define CISS_CMD_STATUS_ABORTED 8
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#define CISS_CMD_STATUS_ABORT_FAILED 9
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#define CISS_CMD_STATUS_UNSOLICITED_ABORT 10
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#define CISS_CMD_STATUS_TIMEOUT 11
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#define CISS_CMD_STATUS_UNABORTABLE 12
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u_int32_t residual_count;
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union {
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struct {
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u_int8_t res1[3];
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u_int8_t type;
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u_int32_t error_info;
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} common_info __packed;
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struct {
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u_int8_t res1[2];
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u_int8_t offense_size;
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u_int8_t offense_offset;
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u_int32_t offense_value;
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} invalid_command __packed;
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} additional_error_info;
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u_int8_t sense_info[0];
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} __packed;
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struct ciss_sg_entry
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{
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u_int64_t address;
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#define CISS_SG_ADDRESS_BITBUCKET (~(u_int64_t)0)
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u_int32_t length;
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u_int32_t :31;
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u_int32_t extension:1; /* address points to another s/g chain */
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} __packed;
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struct ciss_command
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{
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struct ciss_header header;
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struct ciss_cdb cdb;
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struct ciss_error_info_pointer error_info;
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struct ciss_sg_entry sg[0];
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} __packed;
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#define CISS_OPCODE_REPORT_LOGICAL_LUNS 0xc2
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#define CISS_OPCODE_REPORT_PHYSICAL_LUNS 0xc3
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struct ciss_lun_report
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{
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u_int32_t list_size; /* big-endian */
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u_int32_t :32;
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union ciss_device_address lun[0];
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} __packed;
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#define CISS_VPD_LOGICAL_DRIVE_GEOMETRY 0xc1
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struct ciss_ldrive_geometry
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{
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u_int8_t periph_qualifier:3;
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u_int8_t periph_devtype:5;
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u_int8_t page_code;
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u_int8_t res1;
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u_int8_t page_length;
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u_int16_t cylinders; /* big-endian */
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u_int8_t heads;
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u_int8_t sectors;
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u_int8_t fault_tolerance;
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u_int8_t res2[3];
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} __attribute__ ((packed));
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struct ciss_report_cdb
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{
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u_int8_t opcode;
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u_int8_t reserved[5];
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u_int32_t length; /* big-endian */
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u_int8_t :8;
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u_int8_t control;
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} __packed;
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/*
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* Note that it's not clear whether we have to set the detail field to
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* the tag of the command to be aborted, or the tag field in the command itself;
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* documentation conflicts on this.
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*/
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#define CISS_OPCODE_MESSAGE_ABORT 0x00
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#define CISS_MESSAGE_ABORT_TASK 0x00
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#define CISS_MESSAGE_ABORT_TASK_SET 0x01
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#define CISS_MESSAGE_ABORT_CLEAR_ACA 0x02
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#define CISS_MESSAGE_ABORT_CLEAR_TASK_SET 0x03
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#define CISS_OPCODE_MESSAGE_RESET 0x01
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#define CISS_MESSAGE_RESET_CONTROLLER 0x00
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#define CISS_MESSAGE_RESET_BUS 0x01
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#define CISS_MESSAGE_RESET_TARGET 0x03
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#define CISS_MESSAGE_RESET_LOGICAL_UNIT 0x04
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#define CISS_OPCODE_MESSAGE_SCAN 0x02
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#define CISS_MESSAGE_SCAN_CONTROLLER 0x00
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#define CISS_MESSAGE_SCAN_BUS 0x01
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#define CISS_MESSAGE_SCAN_TARGET 0x03
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#define CISS_MESSAGE_SCAN_LOGICAL_UNIT 0x04
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#define CISS_OPCODE_MESSAGE_NOP 0x03
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struct ciss_message_cdb
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{
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u_int8_t opcode;
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u_int8_t type;
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u_int16_t :16;
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u_int32_t abort_tag; /* XXX endianness? */
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u_int8_t reserved[8];
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} __packed;
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/*
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* CISS vendor-specific commands/messages.
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*
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* Note that while messages and vendor-specific commands are
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* differentiated, they are handled in basically the same way and can
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* be considered to be basically the same thing, as long as the cdb
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* type field is set correctly.
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*/
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#define CISS_OPCODE_READ 0xc0
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#define CISS_OPCODE_WRITE 0xc1
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#define CISS_COMMAND_NOTIFY_ON_EVENT 0xd0
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#define CISS_COMMAND_ABORT_NOTIFY 0xd1
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struct ciss_notify_cdb
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{
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u_int8_t opcode;
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u_int8_t command;
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u_int8_t res1[2];
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u_int16_t timeout; /* seconds, little-endian */
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u_int8_t res2; /* reserved */
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u_int8_t synchronous:1; /* return immediately */
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u_int8_t ordered:1; /* return events in recorded order */
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u_int8_t seek_to_oldest:1; /* reset read counter to oldest event */
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u_int8_t new_only:1; /* ignore any queued events */
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u_int8_t :4;
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u_int32_t length; /* must be 512, little-endian */
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#define CISS_NOTIFY_DATA_SIZE 512
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u_int8_t control;
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} __packed;
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#define CISS_NOTIFY_NOTIFIER 0
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#define CISS_NOTIFY_NOTIFIER_STATUS 0
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#define CISS_NOTIFY_NOTIFIER_PROTOCOL 1
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#define CISS_NOTIFY_HOTPLUG 1
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#define CISS_NOTIFY_HOTPLUG_PHYSICAL 0
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#define CISS_NOTIFY_HOTPLUG_POWERSUPPLY 1
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#define CISS_NOTIFY_HOTPLUG_FAN 2
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#define CISS_NOTIFY_HOTPLUG_POWER 3
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#define CISS_NOTIFY_HOTPLUG_REDUNDANT 4
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#define CISS_NOTIFY_HARDWARE 2
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#define CISS_NOTIFY_HARDWARE_CABLES 0
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#define CISS_NOTIFY_HARDWARE_MEMORY 1
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#define CISS_NOTIFY_HARDWARE_FAN 2
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#define CISS_NOTIFY_HARDWARE_VRM 3
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#define CISS_NOTIFY_ENVIRONMENT 3
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#define CISS_NOTIFY_ENVIRONMENT_TEMPERATURE 0
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#define CISS_NOTIFY_ENVIRONMENT_POWERSUPPLY 1
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#define CISS_NOTIFY_ENVIRONMENT_CHASSIS 2
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#define CISS_NOTIFY_ENVIRONMENT_POWER 3
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#define CISS_NOTIFY_PHYSICAL 4
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#define CISS_NOTIFY_PHYSICAL_STATE 0
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#define CISS_NOTIFY_LOGICAL 5
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#define CISS_NOTIFY_LOGICAL_STATUS 0
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#define CISS_NOTIFY_LOGICAL_ERROR 1
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#define CISS_NOTIFY_LOGICAL_SURFACE 2
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#define CISS_NOTIFY_REDUNDANT 6
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#define CISS_NOTIFY_REDUNDANT_STATUS 0
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#define CISS_NOTIFY_CISS 8
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#define CISS_NOTIFY_CISS_REDUNDANT_CHANGE 0
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#define CISS_NOTIFY_CISS_PATH_STATUS 1
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#define CISS_NOTIFY_CISS_HARDWARE_ERROR 2
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#define CISS_NOTIFY_CISS_LOGICAL 3
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struct ciss_notify_drive
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{
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u_int16_t physical_drive_number;
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u_int8_t configured_drive_flag;
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u_int8_t spare_drive_flag;
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u_int8_t big_physical_drive_number;
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u_int8_t enclosure_bay_number;
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} __packed;
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struct ciss_notify_locator
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{
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u_int16_t port;
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u_int16_t id;
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u_int16_t box;
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} __packed;
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struct ciss_notify_redundant_controller
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{
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u_int16_t slot;
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} __packed;
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struct ciss_notify_logical_status
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{
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u_int16_t logical_drive;
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u_int8_t previous_state;
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u_int8_t new_state;
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u_int8_t spare_state;
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} __packed;
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struct ciss_notify_rebuild_aborted
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{
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u_int16_t logical_drive;
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u_int8_t replacement_drive;
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u_int8_t error_drive;
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u_int8_t big_replacement_drive;
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u_int8_t big_error_drive;
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} __packed;
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struct ciss_notify_io_error
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{
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u_int16_t logical_drive;
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u_int32_t lba;
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u_int16_t block_count;
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u_int8_t command;
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u_int8_t failure_bus;
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u_int8_t failure_drive;
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u_int64_t big_lba;
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} __packed;
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struct ciss_notify_consistency_completed
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{
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u_int16_t logical_drive;
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} __packed;
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struct ciss_notify
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{
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u_int32_t timestamp; /* seconds since controller power-on */
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u_int16_t class;
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u_int16_t subclass;
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u_int16_t detail;
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union
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{
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struct ciss_notify_drive drive;
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struct ciss_notify_locator location;
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struct ciss_notify_redundant_controller redundant_controller;
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struct ciss_notify_logical_status logical_status;
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struct ciss_notify_rebuild_aborted rebuild_aborted;
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struct ciss_notify_io_error io_error;
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struct ciss_notify_consistency_completed consistency_completed;
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u_int8_t data[64];
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} data;
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char message[80];
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u_int32_t tag;
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u_int16_t date;
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u_int16_t year;
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u_int32_t time;
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u_int16_t pre_power_up_time;
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union ciss_device_address device;
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/* XXX pads to 512 bytes */
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} __packed;
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/*
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* CISS config table, which describes the controller's
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* supported interface(s) and capabilities.
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*
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* This is mapped directly via PCI.
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*/
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struct ciss_config_table
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{
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char signature[4]; /* "CISS" */
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u_int32_t valence;
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#define CISS_MIN_VALENCE 1 /* only value currently supported */
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#define CISS_MAX_VALENCE 1
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u_int32_t supported_methods;
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#define CISS_TRANSPORT_METHOD_READY (1<<0)
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#define CISS_TRANSPORT_METHOD_SIMPLE (1<<1)
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u_int32_t active_method;
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u_int32_t requested_method;
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u_int32_t command_physlimit;
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u_int32_t interrupt_coalesce_delay;
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u_int32_t interrupt_coalesce_count;
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u_int32_t max_outstanding_commands;
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u_int32_t bus_types;
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#define CISS_TRANSPORT_BUS_TYPE_ULTRA2 (1<<0)
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#define CISS_TRANSPORT_BUS_TYPE_ULTRA3 (1<<1)
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#define CISS_TRANSPORT_BUS_TYPE_FIBRE1 (1<<8)
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#define CISS_TRANSPORT_BUS_TYPE_FIBRE2 (1<<9)
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u_int32_t host_driver;
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#define CISS_DRIVER_SUPPORT_UNIT_ATTENTION (1<<0)
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#define CISS_DRIVER_QUICK_INIT (1<<1)
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#define CISS_DRIVER_INTERRUPT_ON_LOCKUP (1<<2)
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#define CISS_DRIVER_SUPPORT_MIXED_Q_TAGS (1<<3)
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#define CISS_DRIVER_HOST_IS_ALPHA (1<<4)
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char server_name[16];
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u_int32_t heartbeat;
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} __packed;
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/*
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* In a flagrant violation of what CISS seems to be meant to be about,
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* Compaq recycle a goodly portion of their previous generation's
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* command set (and all the legacy baggage related to a design
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* originally aimed at narrow SCSI) through the Array Controller Read
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* and Array Controller Write interface.
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*
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* Command ID values here can be looked up for in the
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* publically-available documentation for the older controllers; note
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* that the command layout is necessarily different to fit within the
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* CDB.
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*/
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#define CISS_ARRAY_CONTROLLER_READ 0x26
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#define CISS_ARRAY_CONTROLLER_WRITE 0x27
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#define CISS_BMIC_ID_LDRIVE 0x10
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#define CISS_BMIC_ID_CTLR 0x11
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#define CISS_BMIC_ID_LSTATUS 0x12
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#define CISS_BMIC_ID_PDRIVE 0x15
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#define CISS_BMIC_BLINK_PDRIVE 0x16
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#define CISS_BMIC_SENSE_BLINK_PDRIVE 0x17
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#define CISS_BMIC_FLUSH_CACHE 0xc2
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#define CISS_BMIC_ACCEPT_MEDIA 0xe0
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/*
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* When numbering drives, the original design assumed that
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* drives 0-7 are on the first SCSI bus, 8-15 on the second,
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* and so forth. In order to handle modern SCSI configurations,
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* the MSB is set in the drive ID field, in which case the
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* modulus changes from 8 to the number of supported drives
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* per SCSI bus (as obtained from the ID_CTLR command).
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* This feature is referred to as BIG_MAP support, and we assume
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* that all CISS controllers support it.
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*/
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#define CISS_BIG_MAP_ID(sc, bus, target) \
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(0x80 | \
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((sc)->ciss_id->drives_per_scsi_bus * (bus)) | \
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(target))
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#define CISS_BIG_MAP_BUS(sc, id) \
|
|
(((id) & 0x80) ? (((id) & ~0x80) / (sc)->ciss_id->drives_per_scsi_bus) : -1)
|
|
|
|
#define CISS_BIG_MAP_TARGET(sc, id) \
|
|
(((id) & 0x80) ? (((id) & ~0x80) % (sc)->ciss_id->drives_per_scsi_bus) : -1)
|
|
|
|
#define CISS_BIG_MAP_ENTRIES 128 /* number of entries in a BIG_MAP */
|
|
|
|
/*
|
|
* BMIC CDB
|
|
*
|
|
* Note that the phys_drive/res1 field is nominally the 32-bit
|
|
* "block number" field, but the only BMIC command(s) of interest
|
|
* implemented overload the MSB (note big-endian format here)
|
|
* to be the physical drive ID, so we define accordingly.
|
|
*/
|
|
struct ciss_bmic_cdb {
|
|
u_int8_t opcode;
|
|
u_int8_t log_drive;
|
|
u_int8_t phys_drive;
|
|
u_int8_t res1[3];
|
|
u_int8_t bmic_opcode;
|
|
u_int16_t size; /* big-endian */
|
|
u_int8_t res2;
|
|
} __packed;
|
|
|
|
/*
|
|
* BMIC command command/return structures.
|
|
*/
|
|
|
|
/* CISS_BMIC_ID_LDRIVE */
|
|
struct ciss_bmic_id_ldrive {
|
|
u_int16_t block_size;
|
|
u_int32_t blocks_available;
|
|
u_int8_t drive_parameter_table[16]; /* XXX define */
|
|
u_int8_t fault_tolerance;
|
|
#define CISS_LDRIVE_RAID0 0
|
|
#define CISS_LDRIVE_RAID4 1
|
|
#define CISS_LDRIVE_RAID1 2
|
|
#define CISS_LDRIVE_RAID5 3
|
|
u_int8_t res1[2];
|
|
#if 0 /* only for identify logical drive extended (0x18) */
|
|
u_int32_t logical_drive_identifier;
|
|
char logical_drive_label[64];
|
|
#endif
|
|
} __packed;
|
|
|
|
/* CISS_BMIC_ID_LSTATUS */
|
|
struct ciss_bmic_id_lstatus {
|
|
u_int8_t status;
|
|
#define CISS_LSTATUS_OK 0
|
|
#define CISS_LSTATUS_FAILED 1
|
|
#define CISS_LSTATUS_NOT_CONFIGURED 2
|
|
#define CISS_LSTATUS_INTERIM_RECOVERY 3
|
|
#define CISS_LSTATUS_READY_RECOVERY 4
|
|
#define CISS_LSTATUS_RECOVERING 5
|
|
#define CISS_LSTATUS_WRONG_PDRIVE 6
|
|
#define CISS_LSTATUS_MISSING_PDRIVE 7
|
|
#define CISS_LSTATUS_EXPANDING 10
|
|
#define CISS_LSTATUS_BECOMING_READY 11
|
|
#define CISS_LSTATUS_QUEUED_FOR_EXPANSION 12
|
|
u_int32_t deprecated_drive_failure_map;
|
|
u_int8_t res1[416];
|
|
u_int32_t blocks_to_recover;
|
|
u_int8_t deprecated_drive_rebuilding;
|
|
u_int16_t deprecated_remap_count[32];
|
|
u_int32_t deprecated_replacement_map;
|
|
u_int32_t deprecated_active_spare_map;
|
|
u_int8_t spare_configured:1;
|
|
u_int8_t spare_rebuilding:1;
|
|
u_int8_t spare_rebuilt:1;
|
|
u_int8_t spare_failed:1;
|
|
u_int8_t spare_switched:1;
|
|
u_int8_t spare_available:1;
|
|
u_int8_t res2:2;
|
|
u_int8_t deprecated_spare_to_replace_map[32];
|
|
u_int32_t deprecated_replaced_marked_ok_map;
|
|
u_int8_t media_exchanged;
|
|
u_int8_t cache_failure;
|
|
u_int8_t expand_failure;
|
|
u_int8_t rebuild_read_failure:1;
|
|
u_int8_t rebuild_write_failure:1;
|
|
u_int8_t res3:6;
|
|
u_int8_t drive_failure_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int16_t remap_count[CISS_BIG_MAP_ENTRIES];
|
|
u_int8_t replacement_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int8_t active_spare_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int8_t spare_to_replace_map[CISS_BIG_MAP_ENTRIES];
|
|
u_int8_t replaced_marked_ok_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int8_t drive_rebuilding;
|
|
} __packed;
|
|
|
|
/* CISS_BMIC_ID_CTLR */
|
|
struct ciss_bmic_id_table {
|
|
u_int8_t configured_logical_drives;
|
|
u_int32_t config_signature;
|
|
char running_firmware_revision[4];
|
|
char stored_firmware_revision[4];
|
|
u_int8_t hardware_revision;
|
|
u_int8_t res1[4];
|
|
u_int32_t deprecated_drive_present_map;
|
|
u_int32_t deprecated_external_drive_present_map;
|
|
u_int32_t board_id;
|
|
u_int8_t res2;
|
|
u_int32_t deprecated_non_disk_map;
|
|
u_int8_t res3[5];
|
|
char marketting_revision;
|
|
u_int8_t res4:3;
|
|
u_int8_t more_than_seven_supported:1;
|
|
u_int8_t res5:3;
|
|
u_int8_t big_map_supported:1; /* must be set! */
|
|
u_int8_t res6[2];
|
|
u_int8_t scsi_bus_count;
|
|
u_int32_t res7;
|
|
u_int32_t controller_clock;
|
|
u_int8_t drives_per_scsi_bus;
|
|
u_int8_t big_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int8_t big_external_drive_present_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
u_int8_t big_non_disk_map[CISS_BIG_MAP_ENTRIES / 8];
|
|
} __packed;
|
|
|
|
/* CISS_BMIC_ID_PDRIVE */
|
|
struct ciss_bmic_id_pdrive {
|
|
u_int8_t scsi_bus;
|
|
u_int8_t scsi_id;
|
|
u_int16_t block_size;
|
|
u_int32_t total_blocks;
|
|
u_int32_t reserved_blocks;
|
|
char model[40];
|
|
char serial[40];
|
|
char revision[8];
|
|
u_int8_t inquiry_bits;
|
|
u_int8_t res1[2];
|
|
u_int8_t drive_present:1;
|
|
u_int8_t non_disk:1;
|
|
u_int8_t wide:1;
|
|
u_int8_t synchronous:1;
|
|
u_int8_t narrow:1;
|
|
u_int8_t wide_downgraded_to_narrow:1;
|
|
u_int8_t ultra:1;
|
|
u_int8_t ultra2:1;
|
|
u_int8_t SMART:1;
|
|
u_int8_t SMART_errors_recorded:1;
|
|
u_int8_t SMART_errors_enabled:1;
|
|
u_int8_t SMART_errors_detected:1;
|
|
u_int8_t external:1;
|
|
u_int8_t configured:1;
|
|
u_int8_t configured_spare:1;
|
|
u_int8_t cache_saved_enabled:1;
|
|
u_int8_t res2;
|
|
u_int8_t res3:6;
|
|
u_int8_t cache_currently_enabled:1;
|
|
u_int8_t cache_safe:1;
|
|
u_int8_t res4[5];
|
|
char connector[2];
|
|
u_int8_t res5;
|
|
u_int8_t bay;
|
|
} __packed;
|
|
|
|
/* CISS_BMIC_BLINK_PDRIVE */
|
|
/* CISS_BMIC_SENSE_BLINK_PDRIVE */
|
|
struct ciss_bmic_blink_pdrive {
|
|
u_int32_t blink_duration; /* 10ths of a second */
|
|
u_int32_t duration_elapsed; /* only for sense command */
|
|
u_int8_t blinktab[256];
|
|
#define CISS_BMIC_BLINK_ALL 1
|
|
#define CISS_BMIC_BLINK_TIMED 2
|
|
u_int8_t res2[248];
|
|
} __packed;
|
|
|
|
/* CISS_BMIC_FLUSH_CACHE */
|
|
struct ciss_bmic_flush_cache {
|
|
u_int16_t flag;
|
|
#define CISS_BMIC_FLUSH_AND_ENABLE 0
|
|
#define CISS_BMIC_FLUSH_AND_DISABLE 1
|
|
u_int8_t res1[510];
|
|
} __packed;
|
|
|
|
#ifdef _KERNEL
|
|
/*
|
|
* CISS "simple" transport layer.
|
|
*
|
|
* Note that there are two slightly different versions of this interface
|
|
* with different interrupt mask bits. There's nothing like consistency...
|
|
*/
|
|
#define CISS_TL_SIMPLE_BAR_REGS 0x10 /* BAR pointing to register space */
|
|
#define CISS_TL_SIMPLE_BAR_CFG 0x14 /* BAR pointing to space containing config table */
|
|
|
|
#define CISS_TL_SIMPLE_IDBR 0x20 /* inbound doorbell register */
|
|
#define CISS_TL_SIMPLE_IDBR_CFG_TABLE (1<<0) /* notify controller of config table update */
|
|
|
|
#define CISS_TL_SIMPLE_ISR 0x30 /* interrupt status register */
|
|
#define CISS_TL_SIMPLE_IMR 0x34 /* interrupt mask register */
|
|
#define CISS_TL_SIMPLE_INTR_OPQ_SA5 (1<<3) /* OPQ not empty interrupt, SA5 boards */
|
|
#define CISS_TL_SIMPLE_INTR_OPQ_SA5B (1<<2) /* OPQ not empty interrupt, SA5B boards */
|
|
|
|
#define CISS_TL_SIMPLE_IPQ 0x40 /* inbound post queue */
|
|
#define CISS_TL_SIMPLE_OPQ 0x44 /* outbound post queue */
|
|
#define CISS_TL_SIMPLE_OPQ_EMPTY (~(u_int32_t)0)
|
|
|
|
#define CISS_TL_SIMPLE_CFG_BAR 0xb4 /* should be 0x14 */
|
|
#define CISS_TL_SIMPLE_CFG_OFF 0xb8 /* offset in BAR at which config table is located */
|
|
|
|
/*
|
|
* Register access primitives.
|
|
*/
|
|
#define CISS_TL_SIMPLE_READ(sc, ofs) \
|
|
bus_space_read_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs)
|
|
#define CISS_TL_SIMPLE_WRITE(sc, ofs, val) \
|
|
bus_space_write_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs, val)
|
|
|
|
#define CISS_TL_SIMPLE_POST_CMD(sc, phys) CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IPQ, phys)
|
|
#define CISS_TL_SIMPLE_FETCH_CMD(sc) CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_OPQ)
|
|
|
|
/*
|
|
* XXX documentation conflicts with the Linux driver as to whether setting or clearing
|
|
* bits masks interrupts
|
|
*/
|
|
#define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \
|
|
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
|
|
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask)
|
|
#define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \
|
|
CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \
|
|
CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask)
|
|
|
|
#define CISS_TL_SIMPLE_OPQ_INTERRUPT(sc) \
|
|
(CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_ISR) & (sc)->ciss_interrupt_mask)
|
|
|
|
#endif /* _KERNEL */
|