1268 lines
33 KiB
C
1268 lines
33 KiB
C
/*
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* Product specific probe and attach routines for:
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* 3940, 2940, aic7895, aic7890, aic7880,
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* aic7870, aic7860 and aic7850 SCSI controllers
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*
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* Copyright (c) 1995, 1996, 1997, 1998 Justin T. Gibbs
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Where this Software is combined with software released under the terms of
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* the GNU Public License ("GPL") and the terms of the GPL would require the
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* combined work to also be released under the terms of the GPL, the terms
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* and conditions of this License will apply in addition to those of the
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* GPL with the exception of any terms or conditions of this License that
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* conflict with, or are expressly prohibited by, the GPL.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: ahc_pci.c,v 1.9 1999/04/23 23:30:21 gibbs Exp $
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*/
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#include <pci.h>
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#if NPCI > 0
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <pci/pcireg.h>
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#include <pci/pcivar.h>
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#include <machine/bus_memio.h>
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#include <machine/bus_pio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/clock.h>
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#include <sys/rman.h>
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#include <cam/cam.h>
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#include <cam/cam_ccb.h>
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#include <cam/cam_sim.h>
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#include <cam/cam_xpt_sim.h>
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#include <cam/scsi/scsi_all.h>
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#include <dev/aic7xxx/aic7xxx.h>
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#include <dev/aic7xxx/93cx6.h>
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#include <aic7xxx_reg.h>
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#define AHC_PCI_IOADDR PCIR_MAPS /* I/O Address */
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#define AHC_PCI_MEMADDR (PCIR_MAPS + 4) /* Mem I/O Address */
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#define PCI_DEVICE_ID_ADAPTEC_398XU 0x83789004ul
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#define PCI_DEVICE_ID_ADAPTEC_3940U 0x82789004ul
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#define PCI_DEVICE_ID_ADAPTEC_3950U2 0x00509005ul
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#define PCI_DEVICE_ID_ADAPTEC_2944U 0x84789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940U 0x81789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940AU 0x61789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940U2 0x00109005ul
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#define PCI_DEVICE_ID_ADAPTEC_2930U2 0x00119005ul
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#define PCI_DEVICE_ID_ADAPTEC_398X 0x73789004ul
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#define PCI_DEVICE_ID_ADAPTEC_3940 0x72789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2944 0x74789004ul
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#define PCI_DEVICE_ID_ADAPTEC_2940 0x71789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7890 0x001F9005ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7895C 0x78939004ul /* RAID Port */
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#define PCI_DEVICE_ID_ADAPTEC_AIC7895 0x78959004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7896 0x005F9005ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7880 0x80789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7870 0x70789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7860 0x60789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7855 0x55789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7850 0x50789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7810 0x10789004ul
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#define PCI_DEVICE_ID_ADAPTEC_AIC7815 0x15789004ul
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#define AHC_394X_SLOT_CHANNEL_A 4
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#define AHC_394X_SLOT_CHANNEL_B 5
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#define AHC_398X_SLOT_CHANNEL_A 4
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#define AHC_398X_SLOT_CHANNEL_B 8
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#define AHC_398X_SLOT_CHANNEL_C 12
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#define DEVCONFIG 0x40
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#define SCBSIZE32 0x00010000ul /* aic789X only */
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#define MPORTMODE 0x00000400ul /* aic7870 only */
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#define RAMPSM 0x00000200ul /* aic7870 only */
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#define VOLSENSE 0x00000100ul
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#define SCBRAMSEL 0x00000080ul
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#define MRDCEN 0x00000040ul
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#define EXTSCBTIME 0x00000020ul /* aic7870 only */
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#define EXTSCBPEN 0x00000010ul /* aic7870 only */
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#define BERREN 0x00000008ul
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#define DACEN 0x00000004ul
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#define STPWLEVEL 0x00000002ul
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#define DIFACTNEGEN 0x00000001ul /* aic7870 only */
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#define CSIZE_LATTIME 0x0c
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#define CACHESIZE 0x0000003ful /* only 5 bits */
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#define LATTIME 0x0000ff00ul
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static void check_extport(struct ahc_softc *ahc, u_int *sxfrctl1);
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static void configure_termination(struct ahc_softc *ahc,
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struct seeprom_config *sc,
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struct seeprom_descriptor *sd,
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u_int *sxfrctl1);
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static void ahc_ultra2_term_detect(struct ahc_softc *ahc,
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int *enableSEC_low,
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int *enableSEC_high,
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int *enablePRI_low,
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int *enablePRI_high,
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int *eeprom_present);
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static void aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
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int *internal68_present,
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int *externalcable_present,
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int *eeprom_present);
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static void aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
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int *externalcable_present,
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int *eeprom_present);
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static int acquire_seeprom(struct ahc_softc *ahc,
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struct seeprom_descriptor *sd);
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static void release_seeprom(struct seeprom_descriptor *sd);
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static void write_brdctl(struct ahc_softc *ahc, u_int8_t value);
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static u_int8_t read_brdctl(struct ahc_softc *ahc);
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static struct ahc_softc *first_398X;
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static int ahc_pci_probe(device_t dev);
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static int ahc_pci_attach(device_t dev);
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/* Exported for use in the ahc_intr routine */
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void ahc_pci_intr(struct ahc_softc *ahc);
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static device_method_t ahc_pci_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, ahc_pci_probe),
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DEVMETHOD(device_attach, ahc_pci_attach),
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{ 0, 0 }
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};
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static driver_t ahc_pci_driver = {
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"ahc",
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ahc_pci_methods,
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sizeof(struct ahc_softc)
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};
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static devclass_t ahc_devclass;
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DRIVER_MODULE(ahc, pci, ahc_pci_driver, ahc_devclass, 0, 0);
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static int
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ahc_pci_probe(device_t dev)
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{
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const char *name = NULL;
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switch (pci_get_devid(dev)) {
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case PCI_DEVICE_ID_ADAPTEC_398XU:
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name = "Adaptec 398X Ultra SCSI RAID adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_3940U:
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name = "Adaptec 3940 Ultra SCSI host adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_398X:
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name = "Adaptec 398X SCSI RAID adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_3940:
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name = "Adaptec 3940 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_3950U2:
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name = "Adaptec 3950 Ultra2 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2930U2:
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name = "Adaptec 2930 Ultra2 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944U:
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name = "Adaptec 2944 Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940U:
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name = "Adaptec 2940 Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940U2:
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name = "Adaptec 2940 Ultra2 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944:
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name = "Adaptec 2944 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940:
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name = "Adaptec 2940 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_2940AU:
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name = "Adaptec 2940A Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7895:
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name = "Adaptec aic7895 Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7895C:
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name = "Adaptec aic7895 `Raid Port' Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7890:
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name = "Adaptec aic7890/91 Ultra2 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7896:
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name = "Adaptec aic7896/97 Ultra2 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7880:
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name = "Adaptec aic7880 Ultra SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7870:
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name = "Adaptec aic7870 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7860:
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name = "Adaptec aic7860 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7855:
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name = "Adaptec aic7855 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7850:
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name = "Adaptec aic7850 SCSI adapter";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7810:
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name = "Adaptec aic7810 RAID memory controller";
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7815:
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name = "Adaptec aic7815 RAID memory controller";
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break;
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default:
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break;
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}
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if (name != NULL) {
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device_set_desc(dev, name);
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return (0);
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}
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return (ENXIO);
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}
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static int
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ahc_pci_attach(device_t dev)
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{
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bus_dma_tag_t parent_dmat;
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struct resource *regs;
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struct ahc_softc *ahc;
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u_int32_t command;
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struct scb_data *shared_scb_data;
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ahc_chip ahc_t = AHC_NONE;
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ahc_feature ahc_fe = AHC_FENONE;
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ahc_flag ahc_f = AHC_FNONE;
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int regs_type;
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int regs_id;
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u_int our_id = 0;
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u_int sxfrctl1;
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u_int scsiseq;
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int error;
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int zero;
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char channel;
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if (pci_get_function(dev) == 1)
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channel = 'B';
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else
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channel = 'A';
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shared_scb_data = NULL;
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command = pci_read_config(dev, PCIR_COMMAND, /*bytes*/1);
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switch (pci_get_devid(dev)) {
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case PCI_DEVICE_ID_ADAPTEC_398XU:
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case PCI_DEVICE_ID_ADAPTEC_398X:
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if (pci_get_devid(dev) == PCI_DEVICE_ID_ADAPTEC_398XU) {
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ahc_t = AHC_AIC7880;
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ahc_fe = AHC_AIC7880_FE;
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} else {
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ahc_t = AHC_AIC7870;
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ahc_fe = AHC_AIC7870_FE;
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}
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switch (pci_get_slot(dev)) {
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case AHC_398X_SLOT_CHANNEL_A:
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break;
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case AHC_398X_SLOT_CHANNEL_B:
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channel = 'B';
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break;
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case AHC_398X_SLOT_CHANNEL_C:
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channel = 'C';
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break;
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default:
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printf("adapter at unexpected slot %d\n"
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"unable to map to a channel\n",
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pci_get_slot(dev));
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}
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ahc_f |= AHC_LARGE_SEEPROM;
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break;
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case PCI_DEVICE_ID_ADAPTEC_3940U:
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case PCI_DEVICE_ID_ADAPTEC_3940:
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if (pci_get_devid(dev)) {
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ahc_t = AHC_AIC7880;
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ahc_fe = AHC_AIC7880_FE;
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} else {
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ahc_t = AHC_AIC7870;
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ahc_fe = AHC_AIC7870_FE;
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}
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switch (pci_get_slot(dev)) {
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case AHC_394X_SLOT_CHANNEL_A:
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break;
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case AHC_394X_SLOT_CHANNEL_B:
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channel = 'B';
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break;
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default:
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printf("adapter at unexpected slot %d\n"
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"unable to map to a channel\n",
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pci_get_slot(dev));
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}
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7890:
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case PCI_DEVICE_ID_ADAPTEC_2940U2:
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case PCI_DEVICE_ID_ADAPTEC_2930U2:
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{
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ahc_t = AHC_AIC7890;
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ahc_fe = AHC_AIC7890_FE;
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break;
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}
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case PCI_DEVICE_ID_ADAPTEC_AIC7896:
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case PCI_DEVICE_ID_ADAPTEC_3950U2:
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{
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ahc_t = AHC_AIC7896;
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ahc_fe = AHC_AIC7896_FE;
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break;
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}
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case PCI_DEVICE_ID_ADAPTEC_2944U:
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case PCI_DEVICE_ID_ADAPTEC_2940U:
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case PCI_DEVICE_ID_ADAPTEC_AIC7880:
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ahc_t = AHC_AIC7880;
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ahc_fe = AHC_AIC7880_FE;
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break;
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case PCI_DEVICE_ID_ADAPTEC_2944:
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case PCI_DEVICE_ID_ADAPTEC_2940:
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case PCI_DEVICE_ID_ADAPTEC_AIC7870:
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ahc_t = AHC_AIC7870;
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ahc_fe = AHC_AIC7870_FE;
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break;
|
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case PCI_DEVICE_ID_ADAPTEC_2940AU:
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7860:
|
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ahc_fe = AHC_AIC7860_FE;
|
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ahc_t = AHC_AIC7860;
|
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break;
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case PCI_DEVICE_ID_ADAPTEC_AIC7895:
|
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case PCI_DEVICE_ID_ADAPTEC_AIC7895C:
|
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{
|
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u_int32_t devconfig;
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|
|
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ahc_t = AHC_AIC7895;
|
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ahc_fe = AHC_AIC7895_FE;
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devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4);
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devconfig &= ~SCBSIZE32;
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pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4);
|
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break;
|
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}
|
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case PCI_DEVICE_ID_ADAPTEC_AIC7855:
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7850:
|
|
ahc_t = AHC_AIC7850;
|
|
ahc_fe = AHC_AIC7850_FE;
|
|
break;
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7810:
|
|
case PCI_DEVICE_ID_ADAPTEC_AIC7815:
|
|
printf("RAID functionality unsupported\n");
|
|
return (ENXIO);
|
|
default:
|
|
break;
|
|
}
|
|
|
|
regs = NULL;
|
|
regs_type = 0;
|
|
regs_id = 0;
|
|
#ifdef AHC_ALLOW_MEMIO
|
|
if ((command & PCIM_CMD_MEMEN) != 0) {
|
|
regs_type = SYS_RES_MEMORY;
|
|
regs_id = AHC_PCI_MEMADDR;
|
|
regs = bus_alloc_resource(dev, regs_type,
|
|
®s_id, 0, ~0, 1, RF_ACTIVE);
|
|
}
|
|
#endif
|
|
|
|
if (regs == NULL && (command & PCI_COMMAND_IO_ENABLE) != 0) {
|
|
regs_type = SYS_RES_IOPORT;
|
|
regs_id = AHC_PCI_IOADDR;
|
|
regs = bus_alloc_resource(dev, regs_type,
|
|
®s_id, 0, ~0, 1, RF_ACTIVE);
|
|
}
|
|
|
|
if (regs == NULL) {
|
|
device_printf(dev, "can't allocate register resources\n");
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Ensure busmastering is enabled */
|
|
command |= PCIM_CMD_BUSMASTEREN;
|
|
pci_write_config(dev, PCIR_COMMAND, command, /*bytes*/1);
|
|
|
|
/* Allocate a dmatag for our SCB DMA maps */
|
|
/* XXX Should be a child of the PCI bus dma tag */
|
|
error = bus_dma_tag_create(/*parent*/NULL, /*alignment*/0,
|
|
/*boundary*/0,
|
|
/*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
|
|
/*highaddr*/BUS_SPACE_MAXADDR,
|
|
/*filter*/NULL, /*filterarg*/NULL,
|
|
/*maxsize*/MAXBSIZE, /*nsegments*/AHC_NSEG,
|
|
/*maxsegsz*/AHC_MAXTRANSFER_SIZE,
|
|
/*flags*/BUS_DMA_ALLOCNOW, &parent_dmat);
|
|
|
|
if (error != 0) {
|
|
printf("ahc_pci_attach: Could not allocate DMA tag "
|
|
"- error %d\n", error);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* On all PCI adapters, we allow SCB paging */
|
|
ahc_f |= AHC_PAGESCBS;
|
|
if ((ahc = ahc_alloc(dev, regs, regs_type, regs_id, parent_dmat,
|
|
ahc_t|AHC_PCI, ahc_fe, ahc_f,
|
|
shared_scb_data)) == NULL)
|
|
return (ENOMEM);
|
|
|
|
ahc->channel = channel;
|
|
|
|
/* Store our PCI bus information for use in our PCI error handler */
|
|
ahc->device = dev;
|
|
|
|
/* Remeber how the card was setup in case there is no SEEPROM */
|
|
ahc_outb(ahc, HCNTRL, ahc->pause);
|
|
if ((ahc->features & AHC_ULTRA2) != 0)
|
|
our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
|
|
else
|
|
our_id = ahc_inb(ahc, SCSIID) & OID;
|
|
sxfrctl1 = ahc_inb(ahc, SXFRCTL1) & STPWEN;
|
|
scsiseq = ahc_inb(ahc, SCSISEQ);
|
|
|
|
if (ahc_reset(ahc) != 0) {
|
|
/* Failed */
|
|
ahc_free(ahc);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/*
|
|
* Take a look to see if we have external SRAM.
|
|
* We currently do not attempt to use SRAM that is
|
|
* shared among multiple controllers.
|
|
*/
|
|
if ((ahc->features & AHC_ULTRA2) != 0) {
|
|
u_int dscommand0;
|
|
|
|
dscommand0 = ahc_inb(ahc, DSCOMMAND0);
|
|
if ((dscommand0 & RAMPS) != 0) {
|
|
u_int32_t devconfig;
|
|
|
|
devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4);
|
|
if ((devconfig & MPORTMODE) != 0) {
|
|
/* Single user mode */
|
|
|
|
/*
|
|
* XXX Assume 9bit SRAM and enable
|
|
* parity checking
|
|
*/
|
|
devconfig |= EXTSCBPEN;
|
|
pci_write_config(dev, DEVCONFIG,
|
|
devconfig, /*bytes*/4);
|
|
|
|
/*
|
|
* Set the bank select apropriately.
|
|
*/
|
|
if (ahc->channel == 'B')
|
|
ahc_outb(ahc, SCBBADDR, 1);
|
|
else
|
|
ahc_outb(ahc, SCBBADDR, 0);
|
|
|
|
/* Select external SCB SRAM */
|
|
dscommand0 &= ~INTSCBRAMSEL;
|
|
ahc_outb(ahc, DSCOMMAND0, dscommand0);
|
|
|
|
if (ahc_probe_scbs(ahc) == 0) {
|
|
/* External ram isn't really there */
|
|
dscommand0 |= INTSCBRAMSEL;
|
|
ahc_outb(ahc, DSCOMMAND0, dscommand0);
|
|
} else if (bootverbose)
|
|
printf("%s: External SRAM bank%d\n",
|
|
ahc_name(ahc),
|
|
ahc->channel == 'B' ? 1 : 0);
|
|
}
|
|
|
|
}
|
|
} else if ((ahc->chip & AHC_CHIPID_MASK) >= AHC_AIC7870) {
|
|
u_int32_t devconfig;
|
|
|
|
devconfig = pci_read_config(dev, DEVCONFIG, /*bytes*/4);
|
|
if ((devconfig & RAMPSM) != 0
|
|
&& (devconfig & MPORTMODE) != 0) {
|
|
|
|
/* XXX Assume 9bit SRAM and enable parity checking */
|
|
devconfig |= EXTSCBPEN;
|
|
|
|
/* XXX Assume fast SRAM */
|
|
devconfig &= ~EXTSCBTIME;
|
|
|
|
/*
|
|
* Set the bank select apropriately.
|
|
*/
|
|
if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
|
|
if (ahc->channel == 'B')
|
|
ahc_outb(ahc, SCBBADDR, 1);
|
|
else
|
|
ahc_outb(ahc, SCBBADDR, 0);
|
|
}
|
|
|
|
/* Select external SRAM */
|
|
devconfig &= ~SCBRAMSEL;
|
|
pci_write_config(dev, DEVCONFIG, devconfig, /*bytes*/4);
|
|
|
|
if (ahc_probe_scbs(ahc) == 0) {
|
|
/* External ram isn't really there */
|
|
devconfig |= SCBRAMSEL;
|
|
pci_write_config(dev, DEVCONFIG,
|
|
devconfig, /*bytes*/4);
|
|
} else if (bootverbose)
|
|
printf("%s: External SRAM bank%d\n",
|
|
ahc_name(ahc),
|
|
ahc->channel == 'B' ? 1 : 0);
|
|
}
|
|
}
|
|
|
|
zero = 0;
|
|
ahc->irq = bus_alloc_resource(dev, SYS_RES_IRQ, &zero,
|
|
0, ~0, 1, RF_ACTIVE | RF_SHAREABLE);
|
|
if (ahc->irq == NULL) {
|
|
ahc_free(ahc);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
ahc->irq_res_type = SYS_RES_IRQ;
|
|
|
|
/*
|
|
* Do aic7880/aic7870/aic7860/aic7850 specific initialization
|
|
*/
|
|
{
|
|
u_int8_t sblkctl;
|
|
char *id_string;
|
|
|
|
switch(ahc_t) {
|
|
case AHC_AIC7896:
|
|
{
|
|
u_int dscommand0;
|
|
|
|
/*
|
|
* DPARCKEN doesn't work correctly on
|
|
* some MBs so don't use it.
|
|
*/
|
|
id_string = "aic7896/97 ";
|
|
dscommand0 = ahc_inb(ahc, DSCOMMAND0);
|
|
dscommand0 &= ~(USCBSIZE32|DPARCKEN);
|
|
dscommand0 |= CACHETHEN|MPARCKEN;
|
|
ahc_outb(ahc, DSCOMMAND0, dscommand0);
|
|
break;
|
|
}
|
|
case AHC_AIC7890:
|
|
{
|
|
u_int dscommand0;
|
|
|
|
/*
|
|
* DPARCKEN doesn't work correctly on
|
|
* some MBs so don't use it.
|
|
*/
|
|
id_string = "aic7890/91 ";
|
|
dscommand0 = ahc_inb(ahc, DSCOMMAND0);
|
|
dscommand0 &= ~(USCBSIZE32|DPARCKEN);
|
|
dscommand0 |= CACHETHEN|MPARCKEN;
|
|
ahc_outb(ahc, DSCOMMAND0, dscommand0);
|
|
break;
|
|
}
|
|
case AHC_AIC7895:
|
|
id_string = "aic7895 ";
|
|
break;
|
|
case AHC_AIC7880:
|
|
id_string = "aic7880 ";
|
|
break;
|
|
case AHC_AIC7870:
|
|
id_string = "aic7870 ";
|
|
break;
|
|
case AHC_AIC7860:
|
|
id_string = "aic7860 ";
|
|
break;
|
|
case AHC_AIC7850:
|
|
id_string = "aic7850 ";
|
|
break;
|
|
default:
|
|
printf("ahc: Unknown controller type. Ignoring.\n");
|
|
ahc_free(ahc);
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* See if we have an SEEPROM and perform auto-term */
|
|
check_extport(ahc, &sxfrctl1);
|
|
|
|
/*
|
|
* Take the LED out of diagnostic mode
|
|
*/
|
|
sblkctl = ahc_inb(ahc, SBLKCTL);
|
|
ahc_outb(ahc, SBLKCTL, (sblkctl & ~(DIAGLEDEN|DIAGLEDON)));
|
|
|
|
/*
|
|
* I don't know where this is set in the SEEPROM or by the
|
|
* BIOS, so we default to 100% on Ultra or slower controllers
|
|
* and 75% on ULTRA2 controllers.
|
|
*/
|
|
if ((ahc->features & AHC_ULTRA2) != 0) {
|
|
ahc_outb(ahc, DFF_THRSH, RD_DFTHRSH_75|WR_DFTHRSH_75);
|
|
} else {
|
|
ahc_outb(ahc, DSPCISTATUS, DFTHRSH_100);
|
|
}
|
|
|
|
if (ahc->flags & AHC_USEDEFAULTS) {
|
|
/*
|
|
* PCI Adapter default setup
|
|
* Should only be used if the adapter does not have
|
|
* an SEEPROM.
|
|
*/
|
|
/* See if someone else set us up already */
|
|
if (scsiseq != 0) {
|
|
printf("%s: Using left over BIOS settings\n",
|
|
ahc_name(ahc));
|
|
ahc->flags &= ~AHC_USEDEFAULTS;
|
|
} else {
|
|
/*
|
|
* Assume only one connector and always turn
|
|
* on termination.
|
|
*/
|
|
our_id = 0x07;
|
|
sxfrctl1 = STPWEN;
|
|
}
|
|
ahc_outb(ahc, SCSICONF,
|
|
(our_id & 0x07)|ENSPCHK|RESET_SCSI);
|
|
|
|
ahc->our_id = our_id;
|
|
}
|
|
|
|
printf("%s: %s", ahc_name(ahc), id_string);
|
|
}
|
|
|
|
/*
|
|
* Record our termination setting for the
|
|
* generic initialization routine.
|
|
*/
|
|
if ((sxfrctl1 & STPWEN) != 0)
|
|
ahc->flags |= AHC_TERM_ENB_A;
|
|
|
|
if (ahc_init(ahc)) {
|
|
ahc_free(ahc);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* XXX Crude hack - fix sometime */
|
|
if (ahc->flags & AHC_SHARED_SRAM) {
|
|
/* Only set this once we've successfully probed */
|
|
if (shared_scb_data == NULL)
|
|
first_398X = ahc;
|
|
}
|
|
|
|
ahc_attach(ahc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* Check the external port logic for a serial eeprom
|
|
* and termination/cable detection contrls.
|
|
*/
|
|
static void
|
|
check_extport(struct ahc_softc *ahc, u_int *sxfrctl1)
|
|
{
|
|
struct seeprom_descriptor sd;
|
|
struct seeprom_config sc;
|
|
u_int8_t scsi_conf;
|
|
int have_seeprom;
|
|
|
|
sd.sd_tag = ahc->tag;
|
|
sd.sd_bsh = ahc->bsh;
|
|
sd.sd_control_offset = SEECTL;
|
|
sd.sd_status_offset = SEECTL;
|
|
sd.sd_dataout_offset = SEECTL;
|
|
|
|
/*
|
|
* For some multi-channel devices, the c46 is simply too
|
|
* small to work. For the other controller types, we can
|
|
* get our information from either SEEPROM type. Set the
|
|
* type to start our probe with accordingly.
|
|
*/
|
|
if (ahc->flags & AHC_LARGE_SEEPROM)
|
|
sd.sd_chip = C56_66;
|
|
else
|
|
sd.sd_chip = C46;
|
|
|
|
sd.sd_MS = SEEMS;
|
|
sd.sd_RDY = SEERDY;
|
|
sd.sd_CS = SEECS;
|
|
sd.sd_CK = SEECK;
|
|
sd.sd_DO = SEEDO;
|
|
sd.sd_DI = SEEDI;
|
|
|
|
have_seeprom = acquire_seeprom(ahc, &sd);
|
|
|
|
if (have_seeprom) {
|
|
|
|
if (bootverbose)
|
|
printf("%s: Reading SEEPROM...", ahc_name(ahc));
|
|
|
|
for (;;) {
|
|
bus_size_t start_addr;
|
|
|
|
start_addr = 32 * (ahc->channel - 'A');
|
|
|
|
have_seeprom = read_seeprom(&sd, (u_int16_t *)&sc,
|
|
start_addr, sizeof(sc)/2);
|
|
|
|
if (have_seeprom) {
|
|
/* Check checksum */
|
|
int i;
|
|
int maxaddr;
|
|
u_int16_t *scarray;
|
|
u_int16_t checksum;
|
|
|
|
maxaddr = (sizeof(sc)/2) - 1;
|
|
checksum = 0;
|
|
scarray = (u_int16_t *)≻
|
|
|
|
for (i = 0; i < maxaddr; i++)
|
|
checksum = checksum + scarray[i];
|
|
if (checksum == 0 || checksum != sc.checksum) {
|
|
if (bootverbose && sd.sd_chip == C56_66)
|
|
printf ("checksum error\n");
|
|
have_seeprom = 0;
|
|
} else {
|
|
if (bootverbose)
|
|
printf("done.\n");
|
|
break;
|
|
}
|
|
}
|
|
|
|
if (sd.sd_chip == C56_66)
|
|
break;
|
|
sd.sd_chip = C56_66;
|
|
}
|
|
}
|
|
|
|
if (!have_seeprom) {
|
|
if (bootverbose)
|
|
printf("%s: No SEEPROM available.\n", ahc_name(ahc));
|
|
ahc->flags |= AHC_USEDEFAULTS;
|
|
} else {
|
|
/*
|
|
* Put the data we've collected down into SRAM
|
|
* where ahc_init will find it.
|
|
*/
|
|
int i;
|
|
int max_targ = sc.max_targets & CFMAXTARG;
|
|
u_int16_t discenable;
|
|
u_int16_t ultraenb;
|
|
|
|
discenable = 0;
|
|
ultraenb = 0;
|
|
if ((sc.adapter_control & CFULTRAEN) != 0) {
|
|
/*
|
|
* Determine if this adapter has a "newstyle"
|
|
* SEEPROM format.
|
|
*/
|
|
for (i = 0; i < max_targ; i++) {
|
|
if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0){
|
|
ahc->flags |= AHC_NEWEEPROM_FMT;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
for (i = 0; i < max_targ; i++) {
|
|
u_int scsirate;
|
|
u_int16_t target_mask;
|
|
|
|
target_mask = 0x01 << i;
|
|
if (sc.device_flags[i] & CFDISC)
|
|
discenable |= target_mask;
|
|
if ((ahc->flags & AHC_NEWEEPROM_FMT) != 0) {
|
|
if ((sc.device_flags[i] & CFSYNCHISULTRA) != 0)
|
|
ultraenb |= target_mask;
|
|
} else if ((sc.adapter_control & CFULTRAEN) != 0) {
|
|
ultraenb |= target_mask;
|
|
}
|
|
if ((sc.device_flags[i] & CFXFER) == 0x04
|
|
&& (ultraenb & target_mask) != 0) {
|
|
/* Treat 10MHz as a non-ultra speed */
|
|
sc.device_flags[i] &= ~CFXFER;
|
|
ultraenb &= ~target_mask;
|
|
}
|
|
if ((ahc->features & AHC_ULTRA2) != 0) {
|
|
u_int offset;
|
|
|
|
if (sc.device_flags[i] & CFSYNCH)
|
|
offset = MAX_OFFSET_ULTRA2;
|
|
else
|
|
offset = 0;
|
|
ahc_outb(ahc, TARG_OFFSET + i, offset);
|
|
|
|
scsirate = (sc.device_flags[i] & CFXFER)
|
|
| ((ultraenb & target_mask)
|
|
? 0x18 : 0x10);
|
|
if (sc.device_flags[i] & CFWIDEB)
|
|
scsirate |= WIDEXFER;
|
|
} else {
|
|
scsirate = (sc.device_flags[i] & CFXFER) << 4;
|
|
if (sc.device_flags[i] & CFSYNCH)
|
|
scsirate |= SOFS;
|
|
if (sc.device_flags[i] & CFWIDEB)
|
|
scsirate |= WIDEXFER;
|
|
}
|
|
ahc_outb(ahc, TARG_SCSIRATE + i, scsirate);
|
|
}
|
|
ahc->our_id = sc.brtime_id & CFSCSIID;
|
|
|
|
scsi_conf = (ahc->our_id & 0x7);
|
|
if (sc.adapter_control & CFSPARITY)
|
|
scsi_conf |= ENSPCHK;
|
|
if (sc.adapter_control & CFRESETB)
|
|
scsi_conf |= RESET_SCSI;
|
|
|
|
if (sc.bios_control & CFEXTEND)
|
|
ahc->flags |= AHC_EXTENDED_TRANS_A;
|
|
if (ahc->features & AHC_ULTRA
|
|
&& (ahc->flags & AHC_NEWEEPROM_FMT) == 0) {
|
|
/* Should we enable Ultra mode? */
|
|
if (!(sc.adapter_control & CFULTRAEN))
|
|
/* Treat us as a non-ultra card */
|
|
ultraenb = 0;
|
|
}
|
|
/* Set SCSICONF info */
|
|
ahc_outb(ahc, SCSICONF, scsi_conf);
|
|
ahc_outb(ahc, DISC_DSB, ~(discenable & 0xff));
|
|
ahc_outb(ahc, DISC_DSB + 1, ~((discenable >> 8) & 0xff));
|
|
ahc_outb(ahc, ULTRA_ENB, ultraenb & 0xff);
|
|
ahc_outb(ahc, ULTRA_ENB + 1, (ultraenb >> 8) & 0xff);
|
|
}
|
|
|
|
if ((ahc->features & AHC_SPIOCAP) != 0) {
|
|
if ((ahc_inb(ahc, SPIOCAP) & SSPIOCPS) != 0) {
|
|
configure_termination(ahc, &sc, &sd, sxfrctl1);
|
|
}
|
|
} else if (have_seeprom) {
|
|
configure_termination(ahc, &sc, &sd, sxfrctl1);
|
|
}
|
|
|
|
release_seeprom(&sd);
|
|
}
|
|
|
|
static void
|
|
configure_termination(struct ahc_softc *ahc,
|
|
struct seeprom_config *sc,
|
|
struct seeprom_descriptor *sd,
|
|
u_int *sxfrctl1)
|
|
{
|
|
int max_targ = sc->max_targets & CFMAXTARG;
|
|
u_int8_t brddat;
|
|
|
|
brddat = 0;
|
|
|
|
/*
|
|
* Update the settings in sxfrctl1 to match the
|
|
*termination settings
|
|
*/
|
|
*sxfrctl1 = 0;
|
|
|
|
/*
|
|
* SEECS must be on for the GALS to latch
|
|
* the data properly. Be sure to leave MS
|
|
* on or we will release the seeprom.
|
|
*/
|
|
SEEPROM_OUTB(sd, sd->sd_MS | sd->sd_CS);
|
|
if ((sc->adapter_control & CFAUTOTERM) != 0
|
|
|| (ahc->features & AHC_ULTRA2) != 0) {
|
|
int internal50_present;
|
|
int internal68_present;
|
|
int externalcable_present;
|
|
int eeprom_present;
|
|
int enableSEC_low;
|
|
int enableSEC_high;
|
|
int enablePRI_low;
|
|
int enablePRI_high;
|
|
|
|
enableSEC_low = 0;
|
|
enableSEC_high = 0;
|
|
enablePRI_low = 0;
|
|
enablePRI_high = 0;
|
|
if (ahc->features & AHC_ULTRA2) {
|
|
ahc_ultra2_term_detect(ahc, &enableSEC_low,
|
|
&enableSEC_high,
|
|
&enablePRI_low,
|
|
&enablePRI_high,
|
|
&eeprom_present);
|
|
if ((sc->adapter_control & CFSEAUTOTERM) == 0) {
|
|
enableSEC_low = (sc->adapter_control & CFSTERM);
|
|
enableSEC_high =
|
|
(sc->adapter_control & CFWSTERM);
|
|
}
|
|
if ((sc->adapter_control & CFAUTOTERM) == 0) {
|
|
enablePRI_low = enablePRI_high =
|
|
(sc->adapter_control & CFLVDSTERM);
|
|
}
|
|
/* Make the table calculations below happy */
|
|
internal50_present = 0;
|
|
internal68_present = 1;
|
|
externalcable_present = 1;
|
|
} else if ((ahc->features & AHC_SPIOCAP) != 0) {
|
|
aic785X_cable_detect(ahc, &internal50_present,
|
|
&externalcable_present,
|
|
&eeprom_present);
|
|
} else {
|
|
aic787X_cable_detect(ahc, &internal50_present,
|
|
&internal68_present,
|
|
&externalcable_present,
|
|
&eeprom_present);
|
|
}
|
|
|
|
if (max_targ <= 8) {
|
|
internal68_present = 0;
|
|
}
|
|
|
|
if (bootverbose) {
|
|
if ((ahc->features & AHC_ULTRA2) == 0) {
|
|
printf("%s: internal 50 cable %s present, "
|
|
"internal 68 cable %s present\n",
|
|
ahc_name(ahc),
|
|
internal50_present ? "is":"not",
|
|
internal68_present ? "is":"not");
|
|
|
|
printf("%s: external cable %s present\n",
|
|
ahc_name(ahc),
|
|
externalcable_present ? "is":"not");
|
|
}
|
|
printf("%s: BIOS eeprom %s present\n",
|
|
ahc_name(ahc), eeprom_present ? "is" : "not");
|
|
|
|
}
|
|
|
|
/*
|
|
* Now set the termination based on what
|
|
* we found.
|
|
* Flash Enable = BRDDAT7
|
|
* Secondary High Term Enable = BRDDAT6
|
|
* Secondary Low Term Enable = BRDDAT5 (7890)
|
|
* Primary High Term Enable = BRDDAT4 (7890)
|
|
*/
|
|
if ((ahc->features & AHC_ULTRA2) == 0
|
|
&& (internal50_present != 0)
|
|
&& (internal68_present != 0)
|
|
&& (externalcable_present != 0)) {
|
|
printf("%s: Illegal cable configuration!!. "
|
|
"Only two connectors on the "
|
|
"adapter may be used at a "
|
|
"time!\n", ahc_name(ahc));
|
|
}
|
|
|
|
if ((max_targ > 8)
|
|
&& ((externalcable_present == 0)
|
|
|| (internal68_present == 0)
|
|
|| (enableSEC_high != 0))) {
|
|
brddat |= BRDDAT6;
|
|
if (bootverbose)
|
|
printf("%s: %sHigh byte termination Enabled\n",
|
|
ahc_name(ahc),
|
|
enableSEC_high ? "Secondary " : "");
|
|
}
|
|
|
|
if (((internal50_present ? 1 : 0)
|
|
+ (internal68_present ? 1 : 0)
|
|
+ (externalcable_present ? 1 : 0)) <= 1
|
|
|| (enableSEC_low != 0)) {
|
|
if ((ahc->features & AHC_ULTRA2) != 0)
|
|
brddat |= BRDDAT5;
|
|
else
|
|
*sxfrctl1 |= STPWEN;
|
|
if (bootverbose)
|
|
printf("%s: %sLow byte termination Enabled\n",
|
|
ahc_name(ahc),
|
|
enableSEC_low ? "Secondary " : "");
|
|
}
|
|
|
|
if (enablePRI_low != 0) {
|
|
*sxfrctl1 |= STPWEN;
|
|
if (bootverbose)
|
|
printf("%s: Primary Low Byte termination "
|
|
"Enabled\n", ahc_name(ahc));
|
|
}
|
|
|
|
if (enablePRI_high != 0) {
|
|
brddat |= BRDDAT4;
|
|
if (bootverbose)
|
|
printf("%s: Primary High Byte "
|
|
"termination Enabled\n",
|
|
ahc_name(ahc));
|
|
}
|
|
|
|
write_brdctl(ahc, brddat);
|
|
|
|
} else {
|
|
if (sc->adapter_control & CFSTERM) {
|
|
if ((ahc->features & AHC_ULTRA2) != 0)
|
|
brddat |= BRDDAT5;
|
|
else
|
|
*sxfrctl1 |= STPWEN;
|
|
|
|
if (bootverbose)
|
|
printf("%s: %sLow byte termination Enabled\n",
|
|
ahc_name(ahc),
|
|
(ahc->features & AHC_ULTRA2) ? "Primary "
|
|
: "");
|
|
}
|
|
|
|
if (sc->adapter_control & CFWSTERM) {
|
|
brddat |= BRDDAT6;
|
|
if (bootverbose)
|
|
printf("%s: %sHigh byte termination Enabled\n",
|
|
ahc_name(ahc),
|
|
(ahc->features & AHC_ULTRA2)
|
|
? "Secondary " : "");
|
|
}
|
|
|
|
write_brdctl(ahc, brddat);
|
|
}
|
|
SEEPROM_OUTB(sd, sd->sd_MS); /* Clear CS */
|
|
}
|
|
|
|
static void
|
|
ahc_ultra2_term_detect(struct ahc_softc *ahc, int *enableSEC_low,
|
|
int *enableSEC_high, int *enablePRI_low,
|
|
int *enablePRI_high, int *eeprom_present)
|
|
{
|
|
u_int8_t brdctl;
|
|
|
|
/*
|
|
* BRDDAT7 = Eeprom
|
|
* BRDDAT6 = Enable Secondary High Byte termination
|
|
* BRDDAT5 = Enable Secondary Low Byte termination
|
|
* BRDDAT4 = Enable Primary low byte termination
|
|
* BRDDAT3 = Enable Primary high byte termination
|
|
*/
|
|
brdctl = read_brdctl(ahc);
|
|
|
|
*eeprom_present = brdctl & BRDDAT7;
|
|
*enableSEC_high = (brdctl & BRDDAT6);
|
|
*enableSEC_low = (brdctl & BRDDAT5);
|
|
*enablePRI_low = (brdctl & BRDDAT4);
|
|
*enablePRI_high = (brdctl & BRDDAT3);
|
|
}
|
|
|
|
static void
|
|
aic787X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
|
|
int *internal68_present, int *externalcable_present,
|
|
int *eeprom_present)
|
|
{
|
|
u_int8_t brdctl;
|
|
|
|
/*
|
|
* First read the status of our cables.
|
|
* Set the rom bank to 0 since the
|
|
* bank setting serves as a multiplexor
|
|
* for the cable detection logic.
|
|
* BRDDAT5 controls the bank switch.
|
|
*/
|
|
write_brdctl(ahc, 0);
|
|
|
|
/*
|
|
* Now read the state of the internal
|
|
* connectors. BRDDAT6 is INT50 and
|
|
* BRDDAT7 is INT68.
|
|
*/
|
|
brdctl = read_brdctl(ahc);
|
|
*internal50_present = !(brdctl & BRDDAT6);
|
|
*internal68_present = !(brdctl & BRDDAT7);
|
|
|
|
/*
|
|
* Set the rom bank to 1 and determine
|
|
* the other signals.
|
|
*/
|
|
write_brdctl(ahc, BRDDAT5);
|
|
|
|
/*
|
|
* Now read the state of the external
|
|
* connectors. BRDDAT6 is EXT68 and
|
|
* BRDDAT7 is EPROMPS.
|
|
*/
|
|
brdctl = read_brdctl(ahc);
|
|
*externalcable_present = !(brdctl & BRDDAT6);
|
|
*eeprom_present = brdctl & BRDDAT7;
|
|
}
|
|
|
|
static void
|
|
aic785X_cable_detect(struct ahc_softc *ahc, int *internal50_present,
|
|
int *externalcable_present, int *eeprom_present)
|
|
{
|
|
u_int8_t brdctl;
|
|
|
|
ahc_outb(ahc, BRDCTL, BRDRW|BRDCS);
|
|
ahc_outb(ahc, BRDCTL, 0);
|
|
brdctl = ahc_inb(ahc, BRDCTL);
|
|
*internal50_present = !(brdctl & BRDDAT5);
|
|
*externalcable_present = !(brdctl & BRDDAT6);
|
|
|
|
*eeprom_present = (ahc_inb(ahc, SPIOCAP) & EEPROM) != 0;
|
|
}
|
|
|
|
static int
|
|
acquire_seeprom(struct ahc_softc *ahc, struct seeprom_descriptor *sd)
|
|
{
|
|
int wait;
|
|
|
|
if ((ahc->features & AHC_SPIOCAP) != 0
|
|
&& (ahc_inb(ahc, SPIOCAP) & SEEPROM) == 0)
|
|
return (0);
|
|
|
|
/*
|
|
* Request access of the memory port. When access is
|
|
* granted, SEERDY will go high. We use a 1 second
|
|
* timeout which should be near 1 second more than
|
|
* is needed. Reason: after the chip reset, there
|
|
* should be no contention.
|
|
*/
|
|
SEEPROM_OUTB(sd, sd->sd_MS);
|
|
wait = 1000; /* 1 second timeout in msec */
|
|
while (--wait && ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0)) {
|
|
DELAY(1000); /* delay 1 msec */
|
|
}
|
|
if ((SEEPROM_STATUS_INB(sd) & sd->sd_RDY) == 0) {
|
|
SEEPROM_OUTB(sd, 0);
|
|
return (0);
|
|
}
|
|
return(1);
|
|
}
|
|
|
|
static void
|
|
release_seeprom(sd)
|
|
struct seeprom_descriptor *sd;
|
|
{
|
|
/* Release access to the memory port and the serial EEPROM. */
|
|
SEEPROM_OUTB(sd, 0);
|
|
}
|
|
|
|
static void
|
|
write_brdctl(ahc, value)
|
|
struct ahc_softc *ahc;
|
|
u_int8_t value;
|
|
{
|
|
u_int8_t brdctl;
|
|
|
|
if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
|
|
brdctl = BRDSTB;
|
|
if (ahc->channel == 'B')
|
|
brdctl |= BRDCS;
|
|
} else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) {
|
|
brdctl = 0;
|
|
} else {
|
|
brdctl = BRDSTB|BRDCS;
|
|
}
|
|
ahc_outb(ahc, BRDCTL, brdctl);
|
|
brdctl |= value;
|
|
ahc_outb(ahc, BRDCTL, brdctl);
|
|
if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890)
|
|
brdctl |= BRDSTB_ULTRA2;
|
|
else
|
|
brdctl &= ~BRDSTB;
|
|
ahc_outb(ahc, BRDCTL, brdctl);
|
|
if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890)
|
|
brdctl = 0;
|
|
else
|
|
brdctl &= ~BRDCS;
|
|
ahc_outb(ahc, BRDCTL, brdctl);
|
|
}
|
|
|
|
static u_int8_t
|
|
read_brdctl(ahc)
|
|
struct ahc_softc *ahc;
|
|
{
|
|
u_int8_t brdctl;
|
|
u_int8_t value;
|
|
|
|
if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7895) {
|
|
brdctl = BRDRW;
|
|
if (ahc->channel == 'B')
|
|
brdctl |= BRDCS;
|
|
} else if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7890) {
|
|
brdctl = BRDRW_ULTRA2;
|
|
} else {
|
|
brdctl = BRDRW|BRDCS;
|
|
}
|
|
ahc_outb(ahc, BRDCTL, brdctl);
|
|
value = ahc_inb(ahc, BRDCTL);
|
|
ahc_outb(ahc, BRDCTL, 0);
|
|
return (value);
|
|
}
|
|
|
|
#define DPE 0x80
|
|
#define SSE 0x40
|
|
#define RMA 0x20
|
|
#define RTA 0x10
|
|
#define STA 0x08
|
|
#define DPR 0x01
|
|
|
|
void
|
|
ahc_pci_intr(struct ahc_softc *ahc)
|
|
{
|
|
u_int8_t status1;
|
|
|
|
status1 = pci_read_config(ahc->device, PCIR_STATUS + 1, /*bytes*/1);
|
|
|
|
if (status1 & DPE) {
|
|
printf("%s: Data Parity Error Detected during address "
|
|
"or write data phase\n", ahc_name(ahc));
|
|
}
|
|
if (status1 & SSE) {
|
|
printf("%s: Signal System Error Detected\n", ahc_name(ahc));
|
|
}
|
|
if (status1 & RMA) {
|
|
printf("%s: Received a Master Abort\n", ahc_name(ahc));
|
|
}
|
|
if (status1 & RTA) {
|
|
printf("%s: Received a Target Abort\n", ahc_name(ahc));
|
|
}
|
|
if (status1 & STA) {
|
|
printf("%s: Signaled a Target Abort\n", ahc_name(ahc));
|
|
}
|
|
if (status1 & DPR) {
|
|
printf("%s: Data Parity Error has been reported via PERR#\n",
|
|
ahc_name(ahc));
|
|
}
|
|
if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) {
|
|
printf("%s: Latched PCIERR interrupt with "
|
|
"no status bits set\n", ahc_name(ahc));
|
|
}
|
|
pci_write_config(ahc->device, PCIR_STATUS + 1, status1, /*bytes*/1);
|
|
|
|
if (status1 & (DPR|RMA|RTA)) {
|
|
ahc_outb(ahc, CLRINT, CLRPARERR);
|
|
}
|
|
}
|
|
|
|
#endif /* NPCI > 0 */
|