522 lines
13 KiB
C
522 lines
13 KiB
C
/*-
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* Copyright (c) 2013 Luiz Otavio O Souza <loos@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/resource.h>
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#include <machine/fdt.h>
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#include <machine/frame.h>
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#include <machine/intr.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include <arm/broadcom/bcm2835/bcm2835_gpio.h>
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#include <arm/broadcom/bcm2835/bcm2835_spireg.h>
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#include <arm/broadcom/bcm2835/bcm2835_spivar.h>
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#include "spibus_if.h"
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static void bcm_spi_intr(void *);
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#ifdef BCM_SPI_DEBUG
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static void
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bcm_spi_printr(device_t dev)
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{
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struct bcm_spi_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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reg = BCM_SPI_READ(sc, SPI_CS);
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device_printf(dev, "CS=%b\n", reg,
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"\20\1CS0\2CS1\3CPHA\4CPOL\7CSPOL"
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"\10TA\11DMAEN\12INTD\13INTR\14ADCS\15REN\16LEN"
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"\21DONE\22RXD\23TXD\24RXR\25RXF\26CSPOL0\27CSPOL1"
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"\30CSPOL2\31DMA_LEN\32LEN_LONG");
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reg = BCM_SPI_READ(sc, SPI_CLK) & SPI_CLK_MASK;
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if (reg % 2)
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reg--;
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if (reg == 0)
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reg = 65536;
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device_printf(dev, "CLK=%uMhz/%d=%luhz\n",
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SPI_CORE_CLK / 1000000, reg, SPI_CORE_CLK / reg);
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reg = BCM_SPI_READ(sc, SPI_DLEN) & SPI_DLEN_MASK;
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device_printf(dev, "DLEN=%d\n", reg);
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reg = BCM_SPI_READ(sc, SPI_LTOH) & SPI_LTOH_MASK;
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device_printf(dev, "LTOH=%d\n", reg);
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reg = BCM_SPI_READ(sc, SPI_DC);
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device_printf(dev, "DC=RPANIC=%#x RDREQ=%#x TPANIC=%#x TDREQ=%#x\n",
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(reg & SPI_DC_RPANIC_MASK) >> SPI_DC_RPANIC_SHIFT,
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(reg & SPI_DC_RDREQ_MASK) >> SPI_DC_RDREQ_SHIFT,
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(reg & SPI_DC_TPANIC_MASK) >> SPI_DC_TPANIC_SHIFT,
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(reg & SPI_DC_TDREQ_MASK) >> SPI_DC_TDREQ_SHIFT);
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}
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#endif
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static void
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bcm_spi_modifyreg(struct bcm_spi_softc *sc, uint32_t off, uint32_t mask,
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uint32_t value)
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{
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uint32_t reg;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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reg = BCM_SPI_READ(sc, off);
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reg &= ~mask;
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reg |= value;
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BCM_SPI_WRITE(sc, off, reg);
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}
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static int
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bcm_spi_clock_proc(SYSCTL_HANDLER_ARGS)
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{
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struct bcm_spi_softc *sc;
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uint32_t clk;
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int error;
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sc = (struct bcm_spi_softc *)arg1;
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BCM_SPI_LOCK(sc);
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clk = BCM_SPI_READ(sc, SPI_CLK);
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BCM_SPI_UNLOCK(sc);
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clk &= 0xffff;
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if (clk == 0)
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clk = 65536;
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clk = SPI_CORE_CLK / clk;
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error = sysctl_handle_int(oidp, &clk, sizeof(clk), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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clk = SPI_CORE_CLK / clk;
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if (clk <= 1)
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clk = 2;
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else if (clk % 2)
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clk--;
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if (clk > 0xffff)
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clk = 0;
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BCM_SPI_LOCK(sc);
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BCM_SPI_WRITE(sc, SPI_CLK, clk);
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BCM_SPI_UNLOCK(sc);
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return (0);
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}
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static int
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bcm_spi_cs_bit_proc(SYSCTL_HANDLER_ARGS, uint32_t bit)
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{
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struct bcm_spi_softc *sc;
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uint32_t reg;
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int error;
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sc = (struct bcm_spi_softc *)arg1;
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BCM_SPI_LOCK(sc);
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reg = BCM_SPI_READ(sc, SPI_CS);
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BCM_SPI_UNLOCK(sc);
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reg = (reg & bit) ? 1 : 0;
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error = sysctl_handle_int(oidp, ®, sizeof(reg), req);
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if (error != 0 || req->newptr == NULL)
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return (error);
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if (reg)
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reg = bit;
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BCM_SPI_LOCK(sc);
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bcm_spi_modifyreg(sc, SPI_CS, bit, reg);
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BCM_SPI_UNLOCK(sc);
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return (0);
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}
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static int
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bcm_spi_cpol_proc(SYSCTL_HANDLER_ARGS)
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{
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return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPOL));
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}
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static int
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bcm_spi_cpha_proc(SYSCTL_HANDLER_ARGS)
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{
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return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CPHA));
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}
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static int
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bcm_spi_cspol0_proc(SYSCTL_HANDLER_ARGS)
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{
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return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL0));
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}
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static int
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bcm_spi_cspol1_proc(SYSCTL_HANDLER_ARGS)
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{
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return (bcm_spi_cs_bit_proc(oidp, arg1, arg2, req, SPI_CS_CSPOL1));
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}
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static void
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bcm_spi_sysctl_init(struct bcm_spi_softc *sc)
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{
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struct sysctl_ctx_list *ctx;
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struct sysctl_oid *tree_node;
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struct sysctl_oid_list *tree;
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/*
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* Add system sysctl tree/handlers.
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*/
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ctx = device_get_sysctl_ctx(sc->sc_dev);
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tree_node = device_get_sysctl_tree(sc->sc_dev);
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tree = SYSCTL_CHILDREN(tree_node);
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "clock",
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CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
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bcm_spi_clock_proc, "IU", "SPI BUS clock frequency");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpol",
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CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
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bcm_spi_cpol_proc, "IU", "SPI BUS clock polarity");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cpha",
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CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
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bcm_spi_cpha_proc, "IU", "SPI BUS clock phase");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol0",
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CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
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bcm_spi_cspol0_proc, "IU", "SPI BUS chip select 0 polarity");
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SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "cspol1",
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CTLFLAG_RW | CTLTYPE_UINT, sc, sizeof(*sc),
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bcm_spi_cspol1_proc, "IU", "SPI BUS chip select 1 polarity");
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}
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static int
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bcm_spi_probe(device_t dev)
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{
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if (!ofw_bus_is_compatible(dev, "broadcom,bcm2835-spi"))
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return (ENXIO);
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device_set_desc(dev, "BCM2708/2835 SPI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_spi_attach(device_t dev)
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{
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struct bcm_spi_softc *sc;
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device_t gpio;
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int i, rid;
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if (device_get_unit(dev) != 0) {
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device_printf(dev, "only one SPI controller supported\n");
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return (ENXIO);
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}
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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/* Configure the GPIO pins to ALT0 function to enable SPI the pins. */
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gpio = devclass_get_device(devclass_find("gpio"), 0);
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if (!gpio) {
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device_printf(dev, "cannot find gpio0\n");
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return (ENXIO);
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}
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for (i = 0; i < nitems(bcm_spi_pins); i++)
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bcm_gpio_set_alternate(gpio, bcm_spi_pins[i], BCM_GPIO_ALT0);
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Hook up our interrupt handler. */
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, bcm_spi_intr, sc, &sc->sc_intrhand)) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot setup the interrupt handler\n");
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return (ENXIO);
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}
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mtx_init(&sc->sc_mtx, "bcm_spi", NULL, MTX_DEF);
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/* Add sysctl nodes. */
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bcm_spi_sysctl_init(sc);
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#ifdef BCM_SPI_DEBUG
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bcm_spi_printr(dev);
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#endif
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/*
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* Enable the SPI controller. Clear the rx and tx FIFO.
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* Defaults to SPI mode 0.
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*/
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BCM_SPI_WRITE(sc, SPI_CS, SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
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/* Set the SPI clock to 500Khz. */
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BCM_SPI_WRITE(sc, SPI_CLK, SPI_CORE_CLK / 500000);
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#ifdef BCM_SPI_DEBUG
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bcm_spi_printr(dev);
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#endif
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device_add_child(dev, "spibus", -1);
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return (bus_generic_attach(dev));
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}
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static int
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bcm_spi_detach(device_t dev)
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{
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struct bcm_spi_softc *sc;
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bus_generic_detach(dev);
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sc = device_get_softc(dev);
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mtx_destroy(&sc->sc_mtx);
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (0);
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}
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static void
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bcm_spi_fill_fifo(struct bcm_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t cs, written;
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uint8_t *data;
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cmd = sc->sc_cmd;
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cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
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while (sc->sc_written < sc->sc_len &&
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cs == (SPI_CS_TA | SPI_CS_TXD)) {
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data = (uint8_t *)cmd->tx_cmd;
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written = sc->sc_written++;
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if (written >= cmd->tx_cmd_sz) {
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data = (uint8_t *)cmd->tx_data;
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written -= cmd->tx_cmd_sz;
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}
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BCM_SPI_WRITE(sc, SPI_FIFO, data[written]);
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cs = BCM_SPI_READ(sc, SPI_CS) & (SPI_CS_TA | SPI_CS_TXD);
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}
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}
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static void
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bcm_spi_drain_fifo(struct bcm_spi_softc *sc)
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{
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struct spi_command *cmd;
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uint32_t cs, read;
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uint8_t *data;
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cmd = sc->sc_cmd;
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cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
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while (sc->sc_read < sc->sc_len && cs == SPI_CS_RXD) {
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data = (uint8_t *)cmd->rx_cmd;
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read = sc->sc_read++;
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if (read >= cmd->rx_cmd_sz) {
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data = (uint8_t *)cmd->rx_data;
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read -= cmd->rx_cmd_sz;
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}
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data[read] = BCM_SPI_READ(sc, SPI_FIFO) & 0xff;
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cs = BCM_SPI_READ(sc, SPI_CS) & SPI_CS_RXD;
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}
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}
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static void
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bcm_spi_intr(void *arg)
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{
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struct bcm_spi_softc *sc;
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sc = (struct bcm_spi_softc *)arg;
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BCM_SPI_LOCK(sc);
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/* Filter stray interrupts. */
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if ((sc->sc_flags & BCM_SPI_BUSY) == 0) {
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BCM_SPI_UNLOCK(sc);
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return;
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}
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/* TX - Fill up the FIFO. */
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bcm_spi_fill_fifo(sc);
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/* RX - Drain the FIFO. */
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bcm_spi_drain_fifo(sc);
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/* Check for end of transfer. */
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if (sc->sc_written == sc->sc_len && sc->sc_read == sc->sc_len) {
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/* Disable interrupts and the SPI engine. */
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bcm_spi_modifyreg(sc, SPI_CS,
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SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
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wakeup(sc->sc_dev);
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}
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BCM_SPI_UNLOCK(sc);
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}
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static int
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bcm_spi_transfer(device_t dev, device_t child, struct spi_command *cmd)
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{
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struct bcm_spi_softc *sc;
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int cs, err;
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sc = device_get_softc(dev);
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KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
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("TX/RX command sizes should be equal"));
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KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
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("TX/RX data sizes should be equal"));
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BCM_SPI_LOCK(sc);
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/* If the controller is in use wait until it is available. */
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while (sc->sc_flags & BCM_SPI_BUSY)
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mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", 0);
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/* Now we have control over SPI controller. */
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sc->sc_flags = BCM_SPI_BUSY;
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/* Clear the FIFO. */
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bcm_spi_modifyreg(sc, SPI_CS,
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SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO,
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SPI_CS_CLEAR_RXFIFO | SPI_CS_CLEAR_TXFIFO);
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/* Get the proper chip select for this child. */
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spibus_get_cs(child, &cs);
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if (cs < 0 || cs > 2) {
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device_printf(dev,
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"Invalid chip select %d requested by %s\n", cs,
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device_get_nameunit(child));
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BCM_SPI_UNLOCK(sc);
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return (EINVAL);
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}
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/* Save a pointer to the SPI command. */
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sc->sc_cmd = cmd;
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sc->sc_read = 0;
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sc->sc_written = 0;
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sc->sc_len = cmd->tx_cmd_sz + cmd->tx_data_sz;
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/*
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* Set the CS for this transaction, enable interrupts and announce
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* we're ready to tx. This will kick off the first interrupt.
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*/
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bcm_spi_modifyreg(sc, SPI_CS,
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SPI_CS_MASK | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD,
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cs | SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD);
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/* Wait for the transaction to complete. */
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err = mtx_sleep(dev, &sc->sc_mtx, 0, "bcm_spi", hz * 2);
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/* Make sure the SPI engine and interrupts are disabled. */
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bcm_spi_modifyreg(sc, SPI_CS, SPI_CS_TA | SPI_CS_INTR | SPI_CS_INTD, 0);
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/* Clear the controller flags. */
|
|
sc->sc_flags = 0;
|
|
|
|
/*
|
|
* Check for transfer timeout. The SPI controller doesn't
|
|
* return errors.
|
|
*/
|
|
if (err == EWOULDBLOCK) {
|
|
device_printf(sc->sc_dev, "SPI error\n");
|
|
err = EIO;
|
|
}
|
|
|
|
BCM_SPI_UNLOCK(sc);
|
|
|
|
return (err);
|
|
}
|
|
|
|
static phandle_t
|
|
bcm_spi_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* We only have one child, the SPI bus, which needs our own node. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static device_method_t bcm_spi_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, bcm_spi_probe),
|
|
DEVMETHOD(device_attach, bcm_spi_attach),
|
|
DEVMETHOD(device_detach, bcm_spi_detach),
|
|
|
|
/* SPI interface */
|
|
DEVMETHOD(spibus_transfer, bcm_spi_transfer),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, bcm_spi_get_node),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t bcm_spi_devclass;
|
|
|
|
static driver_t bcm_spi_driver = {
|
|
"spi",
|
|
bcm_spi_methods,
|
|
sizeof(struct bcm_spi_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(bcm2835_spi, simplebus, bcm_spi_driver, bcm_spi_devclass, 0, 0);
|