ae09ab8f63
possible, and double faults within an SLB trap handler are not. The result is that it possible to take an SLB fault at any time, on any address, for any reason, at any point in the kernel. This lets us do two important things. First, it removes the (soft) 16 GB RAM ceiling on PPC64 as well as any architectural limitations on KVA space. Second, it lets the kernel tolerate poorly designed hypervisors that have a tendency to fail to restore the SLB properly after a hypervisor context switch. MFC after: 6 weeks
758 lines
17 KiB
C
758 lines
17 KiB
C
/*-
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* Copyright (C) 1995, 1996 Wolfgang Solfrank.
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* Copyright (C) 1995, 1996 TooLs GmbH.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by TooLs GmbH.
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* 4. The name of TooLs GmbH may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
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* ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $NetBSD: trap.c,v 1.58 2002/03/04 04:07:35 dbj Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include "opt_hwpmc_hooks.h"
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#include <sys/param.h>
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#include <sys/kdb.h>
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#include <sys/proc.h>
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#include <sys/ktr.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/pioctl.h>
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#include <sys/ptrace.h>
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#include <sys/reboot.h>
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#include <sys/syscall.h>
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#include <sys/sysent.h>
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#include <sys/systm.h>
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#include <sys/uio.h>
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#include <sys/signalvar.h>
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#include <sys/vmmeter.h>
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#ifdef HWPMC_HOOKS
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#include <sys/pmckern.h>
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#endif
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#include <security/audit/audit.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <vm/vm_extern.h>
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#include <vm/vm_param.h>
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#include <vm/vm_kern.h>
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#include <vm/vm_map.h>
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#include <vm/vm_page.h>
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#include <machine/_inttypes.h>
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#include <machine/altivec.h>
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#include <machine/cpu.h>
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#include <machine/db_machdep.h>
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#include <machine/fpu.h>
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#include <machine/frame.h>
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#include <machine/pcb.h>
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#include <machine/pmap.h>
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#include <machine/psl.h>
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#include <machine/trap.h>
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#include <machine/spr.h>
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#include <machine/sr.h>
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static void trap_fatal(struct trapframe *frame);
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static void printtrap(u_int vector, struct trapframe *frame, int isfatal,
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int user);
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static int trap_pfault(struct trapframe *frame, int user);
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static int fix_unaligned(struct thread *td, struct trapframe *frame);
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static int ppc_instr_emulate(struct trapframe *frame);
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static int handle_onfault(struct trapframe *frame);
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static void syscall(struct trapframe *frame);
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#ifdef __powerpc64__
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void handle_kernel_slb_spill(int, register_t, register_t);
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static int handle_user_slb_spill(pmap_t pm, vm_offset_t addr);
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extern int n_slbs;
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#endif
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int setfault(faultbuf); /* defined in locore.S */
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/* Why are these not defined in a header? */
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int badaddr(void *, size_t);
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int badaddr_read(void *, size_t, int *);
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struct powerpc_exception {
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u_int vector;
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char *name;
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};
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static struct powerpc_exception powerpc_exceptions[] = {
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{ 0x0100, "system reset" },
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{ 0x0200, "machine check" },
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{ 0x0300, "data storage interrupt" },
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{ 0x0380, "data segment exception" },
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{ 0x0400, "instruction storage interrupt" },
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{ 0x0480, "instruction segment exception" },
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{ 0x0500, "external interrupt" },
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{ 0x0600, "alignment" },
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{ 0x0700, "program" },
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{ 0x0800, "floating-point unavailable" },
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{ 0x0900, "decrementer" },
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{ 0x0c00, "system call" },
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{ 0x0d00, "trace" },
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{ 0x0e00, "floating-point assist" },
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{ 0x0f00, "performance monitoring" },
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{ 0x0f20, "altivec unavailable" },
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{ 0x1000, "instruction tlb miss" },
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{ 0x1100, "data load tlb miss" },
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{ 0x1200, "data store tlb miss" },
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{ 0x1300, "instruction breakpoint" },
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{ 0x1400, "system management" },
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{ 0x1600, "altivec assist" },
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{ 0x1700, "thermal management" },
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{ 0x2000, "run mode/trace" },
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{ 0x3000, NULL }
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};
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static const char *
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trapname(u_int vector)
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{
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struct powerpc_exception *pe;
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for (pe = powerpc_exceptions; pe->vector != 0x3000; pe++) {
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if (pe->vector == vector)
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return (pe->name);
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}
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return ("unknown");
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}
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void
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trap(struct trapframe *frame)
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{
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struct thread *td;
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struct proc *p;
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int sig, type, user;
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u_int ucode;
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ksiginfo_t ksi;
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PCPU_INC(cnt.v_trap);
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td = curthread;
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p = td->td_proc;
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type = ucode = frame->exc;
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sig = 0;
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user = frame->srr1 & PSL_PR;
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CTR3(KTR_TRAP, "trap: %s type=%s (%s)", td->td_name,
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trapname(type), user ? "user" : "kernel");
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#ifdef HWPMC_HOOKS
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if (type == EXC_PERF && (pmc_intr != NULL)) {
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#ifdef notyet
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(*pmc_intr)(PCPU_GET(cpuid), frame);
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if (!user)
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return;
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#endif
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}
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else
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#endif
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if (user) {
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td->td_pticks = 0;
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td->td_frame = frame;
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if (td->td_ucred != p->p_ucred)
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cred_update_thread(td);
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/* User Mode Traps */
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switch (type) {
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case EXC_RUNMODETRC:
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case EXC_TRC:
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frame->srr1 &= ~PSL_SE;
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sig = SIGTRAP;
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break;
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#ifdef __powerpc64__
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case EXC_ISE:
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case EXC_DSE:
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if (handle_user_slb_spill(&p->p_vmspace->vm_pmap,
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(type == EXC_ISE) ? frame->srr0 :
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frame->cpu.aim.dar) != 0)
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sig = SIGSEGV;
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break;
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#endif
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case EXC_DSI:
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case EXC_ISI:
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sig = trap_pfault(frame, 1);
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break;
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case EXC_SC:
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syscall(frame);
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break;
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case EXC_FPU:
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KASSERT((td->td_pcb->pcb_flags & PCB_FPU) != PCB_FPU,
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("FPU already enabled for thread"));
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enable_fpu(td);
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break;
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case EXC_VEC:
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KASSERT((td->td_pcb->pcb_flags & PCB_VEC) != PCB_VEC,
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("Altivec already enabled for thread"));
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enable_vec(td);
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break;
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case EXC_VECAST_G4:
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case EXC_VECAST_G5:
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/*
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* We get a VPU assist exception for IEEE mode
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* vector operations on denormalized floats.
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* Emulating this is a giant pain, so for now,
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* just switch off IEEE mode and treat them as
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* zero.
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*/
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save_vec(td);
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td->td_pcb->pcb_vec.vscr |= ALTIVEC_VSCR_NJ;
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enable_vec(td);
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break;
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case EXC_ALI:
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if (fix_unaligned(td, frame) != 0)
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sig = SIGBUS;
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else
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frame->srr0 += 4;
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break;
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case EXC_PGM:
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/* Identify the trap reason */
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if (frame->srr1 & EXC_PGM_TRAP)
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sig = SIGTRAP;
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else if (ppc_instr_emulate(frame) == 0)
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frame->srr0 += 4;
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else
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sig = SIGILL;
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break;
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default:
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trap_fatal(frame);
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}
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} else {
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/* Kernel Mode Traps */
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KASSERT(cold || td->td_ucred != NULL,
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("kernel trap doesn't have ucred"));
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switch (type) {
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#ifdef __powerpc64__
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case EXC_DSE:
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if ((frame->cpu.aim.dar & SEGMENT_MASK) == USER_ADDR) {
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__asm __volatile ("slbmte %0, %1" ::
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"r"(td->td_pcb->pcb_cpu.aim.usr_vsid),
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"r"(USER_SLB_SLBE));
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return;
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}
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break;
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#endif
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case EXC_DSI:
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if (trap_pfault(frame, 0) == 0)
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return;
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break;
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case EXC_MCHK:
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if (handle_onfault(frame))
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return;
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break;
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default:
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break;
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}
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trap_fatal(frame);
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}
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if (sig != 0) {
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if (p->p_sysent->sv_transtrap != NULL)
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sig = (p->p_sysent->sv_transtrap)(sig, type);
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ksiginfo_init_trap(&ksi);
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ksi.ksi_signo = sig;
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ksi.ksi_code = (int) ucode; /* XXX, not POSIX */
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/* ksi.ksi_addr = ? */
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ksi.ksi_trapno = type;
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trapsignal(td, &ksi);
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}
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userret(td, frame);
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mtx_assert(&Giant, MA_NOTOWNED);
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}
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static void
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trap_fatal(struct trapframe *frame)
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{
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printtrap(frame->exc, frame, 1, (frame->srr1 & PSL_PR));
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#ifdef KDB
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if ((debugger_on_panic || kdb_active) &&
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kdb_trap(frame->exc, 0, frame))
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return;
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#endif
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panic("%s trap", trapname(frame->exc));
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}
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static void
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printtrap(u_int vector, struct trapframe *frame, int isfatal, int user)
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{
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printf("\n");
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printf("%s %s trap:\n", isfatal ? "fatal" : "handled",
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user ? "user" : "kernel");
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printf("\n");
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printf(" exception = 0x%x (%s)\n", vector, trapname(vector));
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switch (vector) {
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case EXC_DSE:
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case EXC_DSI:
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printf(" virtual address = 0x%" PRIxPTR "\n",
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frame->cpu.aim.dar);
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break;
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case EXC_ISE:
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case EXC_ISI:
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printf(" virtual address = 0x%" PRIxPTR "\n", frame->srr0);
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break;
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}
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printf(" srr0 = 0x%" PRIxPTR "\n", frame->srr0);
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printf(" srr1 = 0x%" PRIxPTR "\n", frame->srr1);
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printf(" lr = 0x%" PRIxPTR "\n", frame->lr);
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printf(" curthread = %p\n", curthread);
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if (curthread != NULL)
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printf(" pid = %d, comm = %s\n",
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curthread->td_proc->p_pid, curthread->td_name);
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printf("\n");
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}
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/*
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* Handles a fatal fault when we have onfault state to recover. Returns
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* non-zero if there was onfault recovery state available.
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*/
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static int
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handle_onfault(struct trapframe *frame)
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{
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struct thread *td;
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faultbuf *fb;
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td = curthread;
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fb = td->td_pcb->pcb_onfault;
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if (fb != NULL) {
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frame->srr0 = (*fb)[0];
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frame->fixreg[1] = (*fb)[1];
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frame->fixreg[2] = (*fb)[2];
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frame->fixreg[3] = 1;
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frame->cr = (*fb)[3];
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bcopy(&(*fb)[4], &frame->fixreg[13],
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19 * sizeof(register_t));
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return (1);
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}
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return (0);
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}
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int
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cpu_fetch_syscall_args(struct thread *td, struct syscall_args *sa)
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{
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struct proc *p;
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struct trapframe *frame;
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caddr_t params;
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size_t argsz;
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int error, n, i;
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p = td->td_proc;
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frame = td->td_frame;
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sa->code = frame->fixreg[0];
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params = (caddr_t)(frame->fixreg + FIRSTARG);
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n = NARGREG;
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if (sa->code == SYS_syscall) {
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/*
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* code is first argument,
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* followed by actual args.
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*/
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sa->code = *(register_t *) params;
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params += sizeof(register_t);
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n -= 1;
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} else if (sa->code == SYS___syscall) {
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/*
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* Like syscall, but code is a quad,
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* so as to maintain quad alignment
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* for the rest of the args.
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*/
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if (SV_PROC_FLAG(p, SV_ILP32)) {
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params += sizeof(register_t);
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sa->code = *(register_t *) params;
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params += sizeof(register_t);
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n -= 2;
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} else {
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sa->code = *(register_t *) params;
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params += sizeof(register_t);
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n -= 1;
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}
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}
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if (p->p_sysent->sv_mask)
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sa->code &= p->p_sysent->sv_mask;
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if (sa->code >= p->p_sysent->sv_size)
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sa->callp = &p->p_sysent->sv_table[0];
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else
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sa->callp = &p->p_sysent->sv_table[sa->code];
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sa->narg = sa->callp->sy_narg;
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if (SV_PROC_FLAG(p, SV_ILP32)) {
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argsz = sizeof(uint32_t);
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for (i = 0; i < n; i++)
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sa->args[i] = ((u_register_t *)(params))[i] &
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0xffffffff;
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} else {
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argsz = sizeof(uint64_t);
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for (i = 0; i < n; i++)
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sa->args[i] = ((u_register_t *)(params))[i];
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}
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if (sa->narg > n)
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error = copyin(MOREARGS(frame->fixreg[1]), sa->args + n,
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(sa->narg - n) * argsz);
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else
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error = 0;
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#ifdef __powerpc64__
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if (SV_PROC_FLAG(p, SV_ILP32) && sa->narg > n) {
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/* Expand the size of arguments copied from the stack */
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for (i = sa->narg; i >= n; i--)
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sa->args[i] = ((uint32_t *)(&sa->args[n]))[i-n];
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}
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#endif
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if (error == 0) {
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td->td_retval[0] = 0;
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td->td_retval[1] = frame->fixreg[FIRSTARG + 1];
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}
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return (error);
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}
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#include "../../kern/subr_syscall.c"
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void
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syscall(struct trapframe *frame)
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{
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struct thread *td;
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struct syscall_args sa;
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int error;
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td = curthread;
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td->td_frame = frame;
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#ifdef __powerpc64__
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/*
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* Speculatively restore last user SLB segment, which we know is
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* invalid already, since we are likely to do copyin()/copyout().
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*/
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__asm __volatile ("slbmte %0, %1; isync" ::
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"r"(td->td_pcb->pcb_cpu.aim.usr_vsid), "r"(USER_SLB_SLBE));
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#endif
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error = syscallenter(td, &sa);
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syscallret(td, error, &sa);
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}
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#ifdef __powerpc64__
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/* Handle kernel SLB faults -- runs in real mode, all seat belts off */
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void
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handle_kernel_slb_spill(int type, register_t dar, register_t srr0)
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{
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struct slb *slbcache;
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uint64_t slbe, slbv;
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uint64_t esid, addr;
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int i;
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addr = (type == EXC_ISE) ? srr0 : dar;
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slbcache = PCPU_GET(slb);
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esid = (uintptr_t)addr >> ADDR_SR_SHFT;
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slbe = (esid << SLBE_ESID_SHIFT) | SLBE_VALID;
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/* See if the hardware flushed this somehow (can happen in LPARs) */
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for (i = 0; i < n_slbs; i++)
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if (slbcache[i].slbe == (slbe | (uint64_t)i))
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return;
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/* Not in the map, needs to actually be added */
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slbv = kernel_va_to_slbv(addr);
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if (slbcache[USER_SLB_SLOT].slbe == 0) {
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for (i = 0; i < n_slbs; i++) {
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if (i == USER_SLB_SLOT)
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continue;
|
|
if (!(slbcache[i].slbe & SLBE_VALID))
|
|
goto fillkernslb;
|
|
}
|
|
|
|
if (i == n_slbs)
|
|
slbcache[USER_SLB_SLOT].slbe = 1;
|
|
}
|
|
|
|
/* Sacrifice a random SLB entry that is not the user entry */
|
|
i = mftb() % n_slbs;
|
|
if (i == USER_SLB_SLOT)
|
|
i = (i+1) % n_slbs;
|
|
|
|
fillkernslb:
|
|
/* Write new entry */
|
|
slbcache[i].slbv = slbv;
|
|
slbcache[i].slbe = slbe | (uint64_t)i;
|
|
|
|
/* Trap handler will restore from cache on exit */
|
|
}
|
|
|
|
static int
|
|
handle_user_slb_spill(pmap_t pm, vm_offset_t addr)
|
|
{
|
|
struct slb *user_entry;
|
|
uint64_t esid;
|
|
int i;
|
|
|
|
esid = (uintptr_t)addr >> ADDR_SR_SHFT;
|
|
|
|
PMAP_LOCK(pm);
|
|
user_entry = user_va_to_slb_entry(pm, addr);
|
|
|
|
if (user_entry == NULL) {
|
|
/* allocate_vsid auto-spills it */
|
|
(void)allocate_user_vsid(pm, esid, 0);
|
|
} else {
|
|
/*
|
|
* Check that another CPU has not already mapped this.
|
|
* XXX: Per-thread SLB caches would be better.
|
|
*/
|
|
for (i = 0; i < pm->pm_slb_len; i++)
|
|
if (pm->pm_slb[i] == user_entry)
|
|
break;
|
|
|
|
if (i == pm->pm_slb_len)
|
|
slb_insert_user(pm, user_entry);
|
|
}
|
|
PMAP_UNLOCK(pm);
|
|
|
|
return (0);
|
|
}
|
|
#endif
|
|
|
|
static int
|
|
trap_pfault(struct trapframe *frame, int user)
|
|
{
|
|
vm_offset_t eva, va;
|
|
struct thread *td;
|
|
struct proc *p;
|
|
vm_map_t map;
|
|
vm_prot_t ftype;
|
|
int rv;
|
|
register_t user_sr;
|
|
|
|
td = curthread;
|
|
p = td->td_proc;
|
|
if (frame->exc == EXC_ISI) {
|
|
eva = frame->srr0;
|
|
ftype = VM_PROT_EXECUTE;
|
|
if (frame->srr1 & SRR1_ISI_PFAULT)
|
|
ftype |= VM_PROT_READ;
|
|
} else {
|
|
eva = frame->cpu.aim.dar;
|
|
if (frame->cpu.aim.dsisr & DSISR_STORE)
|
|
ftype = VM_PROT_WRITE;
|
|
else
|
|
ftype = VM_PROT_READ;
|
|
}
|
|
|
|
if (user) {
|
|
map = &p->p_vmspace->vm_map;
|
|
} else {
|
|
if ((eva >> ADDR_SR_SHFT) == (USER_ADDR >> ADDR_SR_SHFT)) {
|
|
if (p->p_vmspace == NULL)
|
|
return (SIGSEGV);
|
|
|
|
map = &p->p_vmspace->vm_map;
|
|
|
|
user_sr = td->td_pcb->pcb_cpu.aim.usr_segm;
|
|
eva &= ADDR_PIDX | ADDR_POFF;
|
|
eva |= user_sr << ADDR_SR_SHFT;
|
|
} else {
|
|
map = kernel_map;
|
|
}
|
|
}
|
|
va = trunc_page(eva);
|
|
|
|
if (map != kernel_map) {
|
|
/*
|
|
* Keep swapout from messing with us during this
|
|
* critical time.
|
|
*/
|
|
PROC_LOCK(p);
|
|
++p->p_lock;
|
|
PROC_UNLOCK(p);
|
|
|
|
/* Fault in the user page: */
|
|
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
|
|
|
|
PROC_LOCK(p);
|
|
--p->p_lock;
|
|
PROC_UNLOCK(p);
|
|
} else {
|
|
/*
|
|
* Don't have to worry about process locking or stacks in the
|
|
* kernel.
|
|
*/
|
|
rv = vm_fault(map, va, ftype, VM_FAULT_NORMAL);
|
|
}
|
|
|
|
if (rv == KERN_SUCCESS)
|
|
return (0);
|
|
|
|
if (!user && handle_onfault(frame))
|
|
return (0);
|
|
|
|
return (SIGSEGV);
|
|
}
|
|
|
|
int
|
|
badaddr(void *addr, size_t size)
|
|
{
|
|
return (badaddr_read(addr, size, NULL));
|
|
}
|
|
|
|
int
|
|
badaddr_read(void *addr, size_t size, int *rptr)
|
|
{
|
|
struct thread *td;
|
|
faultbuf env;
|
|
int x;
|
|
|
|
/* Get rid of any stale machine checks that have been waiting. */
|
|
__asm __volatile ("sync; isync");
|
|
|
|
td = curthread;
|
|
|
|
if (setfault(env)) {
|
|
td->td_pcb->pcb_onfault = 0;
|
|
__asm __volatile ("sync");
|
|
return 1;
|
|
}
|
|
|
|
__asm __volatile ("sync");
|
|
|
|
switch (size) {
|
|
case 1:
|
|
x = *(volatile int8_t *)addr;
|
|
break;
|
|
case 2:
|
|
x = *(volatile int16_t *)addr;
|
|
break;
|
|
case 4:
|
|
x = *(volatile int32_t *)addr;
|
|
break;
|
|
default:
|
|
panic("badaddr: invalid size (%zd)", size);
|
|
}
|
|
|
|
/* Make sure we took the machine check, if we caused one. */
|
|
__asm __volatile ("sync; isync");
|
|
|
|
td->td_pcb->pcb_onfault = 0;
|
|
__asm __volatile ("sync"); /* To be sure. */
|
|
|
|
/* Use the value to avoid reorder. */
|
|
if (rptr)
|
|
*rptr = x;
|
|
|
|
return (0);
|
|
}
|
|
|
|
/*
|
|
* For now, this only deals with the particular unaligned access case
|
|
* that gcc tends to generate. Eventually it should handle all of the
|
|
* possibilities that can happen on a 32-bit PowerPC in big-endian mode.
|
|
*/
|
|
|
|
static int
|
|
fix_unaligned(struct thread *td, struct trapframe *frame)
|
|
{
|
|
struct thread *fputhread;
|
|
int indicator, reg;
|
|
double *fpr;
|
|
|
|
indicator = EXC_ALI_OPCODE_INDICATOR(frame->cpu.aim.dsisr);
|
|
|
|
switch (indicator) {
|
|
case EXC_ALI_LFD:
|
|
case EXC_ALI_STFD:
|
|
reg = EXC_ALI_RST(frame->cpu.aim.dsisr);
|
|
fpr = &td->td_pcb->pcb_fpu.fpr[reg];
|
|
fputhread = PCPU_GET(fputhread);
|
|
|
|
/* Juggle the FPU to ensure that we've initialized
|
|
* the FPRs, and that their current state is in
|
|
* the PCB.
|
|
*/
|
|
if (fputhread != td) {
|
|
if (fputhread)
|
|
save_fpu(fputhread);
|
|
enable_fpu(td);
|
|
}
|
|
save_fpu(td);
|
|
|
|
if (indicator == EXC_ALI_LFD) {
|
|
if (copyin((void *)frame->cpu.aim.dar, fpr,
|
|
sizeof(double)) != 0)
|
|
return -1;
|
|
enable_fpu(td);
|
|
} else {
|
|
if (copyout(fpr, (void *)frame->cpu.aim.dar,
|
|
sizeof(double)) != 0)
|
|
return -1;
|
|
}
|
|
return 0;
|
|
break;
|
|
}
|
|
|
|
return -1;
|
|
}
|
|
|
|
static int
|
|
ppc_instr_emulate(struct trapframe *frame)
|
|
{
|
|
uint32_t instr;
|
|
int reg;
|
|
|
|
instr = fuword32((void *)frame->srr0);
|
|
|
|
if ((instr & 0xfc1fffff) == 0x7c1f42a6) { /* mfpvr */
|
|
reg = (instr & ~0xfc1fffff) >> 21;
|
|
frame->fixreg[reg] = mfpvr();
|
|
return (0);
|
|
}
|
|
|
|
return (-1);
|
|
}
|
|
|